Chipmakers can use older deep ultraviolet (DUV) lithography to make very small patterns, but doing so often requires multiple exposures and extra processing where extreme ultraviolet (EUV) can print a pattern in one exposure. That makes DUV a poor universal substitute for EUV on the most demanding layers—not an obsolete technology. Leading-edge chips use both: EUV for selected intricate layers and DUV for many others.
Why is EUV harder to replace on the most demanding layers?
The main difference is the light used to project a circuit pattern onto a silicon wafer. ASML lists a wavelength of 13.5 nanometers for EUV and 193 nanometers for its highest-resolution DUV systems. A shorter wavelength supports finer pattern imaging, which helps EUV print intricate layers with fewer patterning operations. ASML’s wavelength comparison
These are not the same scanner with a different bulb. EUV systems use reflective mirrors to direct light; DUV systems use lenses. The optical systems, as well as the processes built around them, differ. ASML’s overview of its lithography products
Can DUV still produce very small features?
Yes. DUV can extend its patterning capability through multi-patterning: rather than expose a dense pattern all at once, a fab divides it across multiple exposures and intervening processing steps. Those operations can produce the desired geometry, but they add complexity to the manufacturing flow.
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That is the practical trade-off. For a layer that needs especially fine patterns, the question is not whether DUV can make them at all; it is whether repeating exposures, masks and processing is practical for the design and the fab’s manufacturing goals. EUV’s shorter wavelength lets manufacturers print some of the most intricate layers with fewer patterning steps. ASML’s EUV systems page
What the process-step estimate does—and does not—mean
ASML’s 2025 annual-report strategy material cites a model estimating around 20% fewer process steps per wafer for EUV single patterning than for DUV multi-patterning. This is a modeled comparison of process steps, not a measured promise of 20% lower total fab cost, higher yield or reduced energy use. ASML’s 2025 annual-report strategy material
The sources do not establish a universal break-even cost, yield or energy figure. Those outcomes depend on the particular process and fab, so the step estimate should not be treated as proof that EUV is always cheaper overall—or that DUV cannot be used for leading-edge patterning.
Why do fabs continue to use DUV?
EUV does not replace every lithography step on a chip. ASML says EUV systems are used for the most intricate layers, while other layers are printed with DUV. It also describes DUV immersion systems working alongside EUV on different layers of the same chip. ASML’s 2025 annual-report strategic report
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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteIn other words, a chip’s manufacturing flow assigns technologies layer by layer. A fab can use EUV where its resolution and patterning advantages matter most, and DUV elsewhere. ASML describes DUV as a cornerstone of the semiconductor industry and EUV as providing the highest resolution in high-volume manufacturing. ASML’s products and services page
What does High-NA EUV change?
High-NA EUV is intended to extend EUV patterning capability. Its numerical aperture (NA) is 0.55, compared with 0.33 for current-generation EUV systems. Higher NA is part of the effort to resolve finer patterns. ASML’s High-NA explainer
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In June 2024, ASML and imec opened a joint lab to give manufacturers an early-development platform for work on process integration, masks, metrology and other ecosystem requirements. The announcement anticipated high-volume manufacturing in the 2025–2026 timeframe. ASML and imec’s June 2024 lab announcement
Separately, ASML’s 2025 annual-report filing says the first TWINSCAN EXE:5200B shipped in early April 2025 ready to be used for high-volume manufacturing. A tool being ready for such use is not evidence that it has been broadly deployed by customers or that mature yields have been achieved across the industry. ASML’s 2025 Annual Report filing
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Why not replace every EUV layer with DUV?
DUV can be pushed further with multi-patterning, but the added exposures and process steps make it a more complicated route for layers that EUV can pattern more directly. EUV is therefore useful where that difference matters; DUV remains useful for the many layers that do not require EUV’s highest resolution. The two technologies are complementary parts of a chipmaking flow, rather than all-or-nothing alternatives.
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