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Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →How are advanced AI chips made? Not in one printing operation. A chip company first defines an architecture and circuit layout, then a foundry builds those designs as hundreds of repeated material-processing steps on silicon wafers. After wafer fabrication, the dies must be separated, connected to memory or other dies in an advanced package, and electrically, thermally and functionally tested before they can ship.
ASML says its general semiconductor flow can involve hundreds of steps and take up to four months from design to mass production. That is a broad company description, not a universal schedule for every product or factory.
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Manufacturing an AI chip means more than making transistors
An advanced AI processor is a chain of coordinated activities:
- Design: engineers define the compute architecture, memory interfaces, interconnects and physical layout.
- Process planning: the design is matched to a particular manufacturing process and its design rules.
- Wafer fabrication: a fab builds transistors and metal interconnects layer by layer on silicon wafers.
- Yield control: inspection and measurement identify defects and adjust the process so more dies on each wafer work.
- Packaging: individual dies are cut from the wafer, connected to substrates, interposers, other dies or high-bandwidth memory, and protected mechanically.
- Assembly and test: finished packages undergo electrical, heat and functional checks before shipment.
For AI and high-performance computing, packaging is part of the product’s architecture. A package may contain several compute dies and stacks of memory linked with extremely fine-pitch connections. A bare wafer die is therefore an intermediate component, not a usable accelerator.
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Who designs and builds the chip?
Fabless chip companies
A fabless company concentrates on architecture, logic design, verification and product software while contracting wafer production to a foundry. ASML identifies Qualcomm, Nvidia and AMD as examples of fabless companies. These businesses still make extensive manufacturing decisions: they select a process, prepare the design for its rules, define performance and power targets, and work with the foundry on yield and ramp-up.
Foundries
A foundry manufactures designs for multiple customers. TSMC is an example cited by ASML. It provides process technology, wafer fabs, design libraries and manufacturing control, while customers supply their own chip layouts. A foundry’s ability to deliver consistent wafers, qualify a process and package complex products can be as important as the advertised node name.
Integrated device manufacturers
An integrated device manufacturer designs and manufactures chips within the same company. The boundaries are not absolute: companies can use a mixture of internal and contracted production, and packaging may be performed at separate facilities or by specialist partners.
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How a design becomes patterns on a silicon wafer
The exact recipes differ by process, but the repeated cycle follows a recognizable order.
- Specify the architecture and physical design. Engineers translate the AI model’s required operations into compute arrays, caches, memory controllers, input/output circuits and power-delivery structures. They then create a geometric layout that a selected process can manufacture.
- Prepare the wafer. A polished silicon wafer provides the starting surface. Modern fabs process many wafers in parallel, with each wafer eventually containing numerous repeated die patterns.
- Deposit a thin film. Equipment adds a controlled layer that may be conductive, insulating or semiconductor material. The film becomes part of a transistor, a contact or an interconnect after later steps.
- Coat the wafer with photoresist. A light-sensitive resist is applied across the wafer. Its chemical behavior will determine which portions remain after exposure and development.
- Expose the pattern with lithography. A reticle carries the circuit image. Lithography projects that image onto the resist, then baking and chemical development create openings in the intended locations.
- Etch the underlying layer. Plasma or chemical etching removes exposed material through the resist openings. The result transfers the reticle’s geometry into the film below.
- Modify electrical properties. Ion implantation and related treatments introduce selected atoms or otherwise alter the material. These changes create regions with the electrical behavior required for transistors and contacts.
- Strip, clean and prepare for the next layer. Used resist is removed and the wafer is cleaned. A new film, resist coating and patterning cycle then begins.
- Measure and inspect. Metrology checks dimensions, alignment, film thickness and other variables. Inspection systems search for particles, pattern defects and process excursions. Results feed back into equipment settings and process control.
This sequence is repeated for many layers. Some layers form the transistor structures; later layers build contacts and a stack of metal wiring that connects billions of devices. Lithography is therefore one step inside a much longer loop, not the whole manufacturing process.
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| Fab activity | What it accomplishes | Why it matters for AI processors |
|---|---|---|
| Deposition | Adds a precisely controlled material film | Creates transistor, dielectric and wiring layers |
| Lithography | Places the geometric pattern in photoresist | Defines small features and layer-to-layer alignment |
| Development and etch | Transfers the resist image into the film | Forms gates, contacts and interconnect structures |
| Implantation and other treatments | Changes material properties | Sets transistor behavior and electrical connections |
| Clean, inspection and metrology | Removes contamination and measures results | Limits defects and improves the number of working dies per wafer |
EUV and DUV: why lithography equipment matters
ASML describes extreme ultraviolet (EUV) lithography as using 13.5-nanometer light for some of the most intricate layers in advanced logic and memory. Deep ultraviolet (DUV) systems remain important for other layers. A leading-edge chip can therefore use multiple lithography technologies in the same manufacturing flow.
The process name alone does not tell you which tool made every layer. It also does not prove that every advanced AI chip uses EUV, or that a particular product uses the newest high-numerical-aperture equipment.
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High-NA EUV is a date-specific milestone
ASML lists a 0.55 numerical aperture for its next-generation EXE High-NA EUV platform. In a release dated July 15, 2026, ASML reported that Intel Foundry was using EXE High NA EUV on Intel 18A to produce a subset of Intel Core Ultra Series 3 processors in high-volume manufacturing. ASML said specified layers had been dual-qualified and that the product was shipping at yields matched to its NXE platform.
That announcement describes one company’s product and process at a particular date. It does not establish that all advanced AI chips use High-NA EUV, that all fabs have the equipment, or that a process-node label identifies a single lithography method.
Yield determines how many chips a wafer really produces
A wafer can contain many die patterns, but defects or out-of-specification features can make individual dies unusable. Yield work begins during process development and continues through volume production. Engineers use inspection and metrology data to locate systematic errors, particles, overlay problems and equipment drift, then tune the process.
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Yield has a direct economic effect: the wafer consumed roughly the same amount of fab time whether it produces a high or low number of usable dies. AI dies are often physically large and contain dense wiring, so a defect can affect a valuable area. Public company announcements may report yield or ramp progress, but those figures need the company, product, process, year and scope attached. They are not automatically industry-wide measurements.
Why advanced packaging is essential to AI hardware
AI accelerators need enormous data movement between compute and memory. Putting every function on one monolithic die is not always the best technical or manufacturing choice. Designers can split logic across dies and place high-bandwidth memory nearby, then connect the pieces in a package.
2.5D integration with an interposer
TSMC describes CoWoS as an advanced 2.5D packaging platform that integrates multiple system-on-chip dies and high-bandwidth memory for high-performance computing and AI. In a 2.5D arrangement, dies sit beside one another on an interposer or comparable high-density connection structure. The package provides far more short, wide connections than a conventional circuit-board assembly.
3D stacking
TSMC describes SoIC as a technology for three-dimensional stacking. Dies are placed vertically and connected with very fine-pitch structures. Stacking can shorten signal paths and increase integration, but it raises alignment, heat-removal, mechanical and test challenges.
Redistribution and other package platforms
TSMC also lists InFO among its advanced packaging technologies. Redistribution layers can reroute connections across a package and help match die-level wiring to a substrate or external interface. The appropriate platform depends on die count, bandwidth, power, thermal limits and the product’s physical dimensions.
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“Packaging” here is not merely a plastic shell. It can include substrates, interposers, redistribution layers, fine-pitch electrical joints, mechanical reinforcement and a thermal path from hot compute dies to a cooler. Intel’s assembly-and-test overview describes a package as providing protection, strength and electrical connections.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Assembly and testing turn dies into shippable products
- Wafer sort: electrical probes check die-level functions while the dies are still attached to the wafer.
- Singulation: the wafer is separated into individual dies.
- Package assembly: dies are attached to a substrate, interposer or other structure and connected to memory or companion dies when required.
- Encapsulation and finishing: the package receives mechanical protection and a controlled thermal path.
- Final tests: electrical, heat and functional tests verify operation under specified conditions before shipment.
Testing must account for the complete package, not only the logic die. Thermal behavior, power delivery, memory links and high-speed interfaces can all affect whether an AI product meets its specification.
How long does the process take?
ASML says the overall manufacturing process can involve hundreds of steps and take up to four months from design to mass production. That statement combines design, process preparation and production in a general explanation. Actual cycle time varies with the product, process maturity, fab loading, rework, inspection requirements, packaging route and qualification schedule.
Mass production also requires a ramp. A first working wafer is not the same as stable, high-volume output. Customers and manufacturers continue measuring defects, electrical distributions, package reliability and test results as production expands.
Resources, emissions and the limits of simple per-chip claims
Advanced fabs consume electricity, water, gases and wet chemicals, but a single universal environmental number per AI chip is not established here. The relevant burden depends on the process, wafer size, number of layers, yield, packaging design, electricity mix and the allocation method used for shared equipment.
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ASML’s 2025 annual-report feature on imec.netzero describes comparisons among chipmaking technologies introduced between 2013 and 2025. Under the model’s assumptions, EUV single patterning can mean around 20% fewer process steps per wafer than DUV multi-patterning, while modeled operational emissions may be approximately 10% lower. Those are scenario results, not guaranteed savings for every fab or product.
“Unlike other models, imec.netzero provides actionable data down to the chip manufacturing process level, allowing projections for future technologies and identification of high-impact processes that contribute the most.”
Emily Gallagher, Program Director at imec, as quoted in ASML’s 2025 annual-report feature
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What public company figures can—and cannot—tell you
TSMC reported 15.0 million 12-inch-equivalent wafer shipments in 2025 and said 74% of its wafer revenue came from advanced technologies of 7 nanometers and beyond. Both figures are TSMC company statistics: the first is its reported shipment total, and the second is its revenue mix. Neither is the share of global AI-chip production, nor a direct measure of how many AI accelerator dies shipped.
Likewise, a vendor-reported production milestone or yield statement should be read with its product, geography, date and process scope. Public sources reviewed here do not establish a neutral ranking of foundries by cost, performance or total yield, and they do not provide a universal manufacturing cost for one advanced AI chip.
A practical framework for comparing manufacturing approaches
When a company announces a new AI-chip process or package, evaluate the claim across these dimensions rather than relying on a node number alone:
| Question | What to look for |
|---|---|
| Is it actually in production? | Distinguish a research demonstration, risk production, qualification, pilot output and high-volume manufacturing. |
| Which lithography is used? | Identify whether EUV, DUV or High-NA EUV applies, and which layers use each approach. |
| How is memory integrated? | Check for conventional mounting, 2.5D interposer integration, 3D stacking or another advanced package. |
| What does the yield claim cover? | Record the company, product, process, date, geography and whether the figure concerns a subset of layers or the complete product. |
| Who is making the assertion? | Separate a vendor’s specification or announcement from an independent measurement. |
| What is not disclosed? | Note missing information about cost, water, electricity, cycle time, package capacity and test limits instead of filling gaps with assumptions. |
The complete picture
Manufacturing an advanced AI chip is a coordinated chain: architectural design, process selection, repeated wafer-layer construction, inspection-driven yield improvement, die separation, advanced package integration and final testing. EUV helps pattern selected intricate layers while DUV remains part of many flows. The finished AI product may depend as much on its interposer, memory connections and thermal design as on the transistors formed in the wafer fab.
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