TSMC’s 2-nanometer-class N2 process entered high-volume manufacturing in the fourth quarter of 2025, and the company expects a fast ramp in 2026. Its next steps include A16 and A14, advanced packaging for AI and high-performance computing, and a planned $265 billion Arizona manufacturing expansion. Intel’s 18A and developing 14A processes are credible competitive responses, but public disclosures do not establish that Intel has overtaken TSMC.
What is TSMC’s next chipmaking node?
N2 is in production; A16 and A14 are next in the roadmap
TSMC’s 2025 annual report says its N2 technology entered high-volume manufacturing in the fourth quarter of 2025, with good yield, and that it expects a fast ramp in 2026. Those are the company’s reported results and plan; the report does not provide a yield percentage or a quantified production target in the material cited here.
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Beyond N2, TSMC lists A16 and A14 in its future process portfolio. The annual report describes A14 as a second-generation nanosheet full-node step after N2. The labels are company-specific names, not standardized measurements that let readers compare transistor dimensions directly across manufacturers.
Derivatives matter alongside headline nodes
The roadmap also includes optimized variants rather than only successive major nodes. TSMC’s official A16 material records N3X entering volume production in 2025 and N3C in 2026. This illustrates why a foundry’s roadmap is broader than a sequence of node names: customers may need particular combinations of performance, power, and design characteristics.
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Can Intel 18A catch TSMC’s N2?
Intel has disclosed a serious leading-edge effort, but the available public milestones do not support a simple winner-takes-all comparison. Intel’s 2025 regulatory filing describes 18A with gate-all-around transistors and backside power delivery, and says 14A is in development using high-NA EUV. The filing also says that competitive leading-edge development requires significant ongoing capital investment.
| Comparison point | TSMC | Intel |
|---|---|---|
| Process milestone | N2 entered high-volume manufacturing in 4Q 2025; TSMC expected a fast 2026 ramp (TSMC 2025 annual report). | 18A and 14A are described in Intel’s 2025 regulatory filing; the material cited here does not state a directly comparable production date or ramp target. |
| Transistor and power approach | A14 is described as a second-generation nanosheet full-node step after N2 (TSMC 2025 annual report). | 18A uses gate-all-around transistors and backside power; 14A development uses high-NA EUV (Intel 2025 regulatory filing). |
| Yield and ramp | TSMC reports good N2 yield and expects a fast 2026 ramp; no yield percentage is stated (TSMC 2025 annual report). | Comparable yield and ramp figures are not stated (Intel 2025 regulatory filing). |
| Advanced packaging | TSMC identifies CoWoS, InFO, SoIC, and silicon-photonics work in its annual-report material. | Comparable packaging capacity figures are not stated in the Intel filing cited here. |
| Customer adoption and cost | Comparable customer-adoption and per-wafer cost figures are not stated in the TSMC material cited here. | Comparable customer-adoption and per-wafer cost figures are not stated in the Intel filing cited here. |
The practical comparison should therefore focus on execution: process timing, yields and ramp speed, power delivery, density, packaging availability, customer adoption, and cost. A company’s node label alone cannot establish which process delivers better results for a given product. Nor do the cited filings establish that Intel has displaced TSMC as the process leader.
Why does advanced packaging matter for AI chips?
AI accelerators depend not only on transistor density but also on how compute, memory, and other components are integrated and connected. Bandwidth and power efficiency can become critical constraints, so packaging capacity is part of the competitive offer rather than a finishing step after fabrication.
TSMC’s annual-report material identifies CoWoS, InFO, and SoIC among its packaging technologies and also highlights silicon-photonics work. The roadmap thus combines process development with 2.5D and 3D integration approaches intended to serve AI and high-performance-computing demand. The cited material does not give comparable capacity or cost figures for each technology, so it cannot establish how much supply will be available to any particular customer.
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TSMC’s Arizona project is now described as a $265 billion plan, expanded from an initial $12 billion project. In July 2026, TSMC announced additional fabs for 2-nanometer-and-below logic and advanced packaging. The $265 billion figure is the stated scale of the plan, not a claim that the full amount has already been spent.
TSMC says the Arizona buildout is intended to scale into an independent GIGAFAB cluster serving smartphone, AI, and high-performance-computing customers. The U.S.-China Economic and Security Review Commission separately reported a 2025 $100 billion expansion announcement and plans for three sub-4nm fabs. These are distinct announcements and descriptions at different points in the project’s evolution; they should not be added together as if they were separate expenditures on top of the $265 billion plan.
What the expansion changes—and what it makes harder
- Geographic reach: More production and packaging in Arizona can put capacity closer to U.S. customers and reduce reliance on a single manufacturing geography.
- Execution demands: Replicating leading-edge yields, supplier ecosystems, and skilled labor across locations is difficult. A larger announced plan is not, by itself, evidence that every facility is built, qualified, or producing at scale.
- Economic trade-off: TSMC’s own account describes heavy continuing R&D investment, while Intel’s filing says leading-edge competition requires significant ongoing capital investment. The cited sources do not provide a like-for-like estimate of the cost or returns of the Arizona buildout.
What demand is TSMC building this roadmap for?
TSMC identifies AI deployments, 5G and 6G, digital transformation, and rising semiconductor content as long-term demand drivers. Its industry-outlook chapter projects approximately 10% compound annual growth for the worldwide semiconductor market excluding memory through 2030. This is a company projection for that market segment, not a guaranteed growth rate for TSMC’s revenue, profits, or shares.
That demand outlook helps explain the linked bets in the roadmap: more advanced logic, packaging for AI and high-performance computing, and capacity outside Taiwan. TSMC says it plans to continue investing heavily in R&D to maintain technology leadership. The commercial payoff still depends on customer demand and on delivering the planned processes and sites with competitive yields, capacity, and economics.
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The information cited here supports a narrower conclusion: TSMC reported N2 entering high-volume manufacturing in 4Q 2025 and set out a broad follow-on plan, while Intel has disclosed 18A and 14A programs that make competition credible. It does not provide a current, source-matched Samsung schedule or enough comparable, independently measured data across all three companies to rank their current manufacturing leadership conclusively.
For readers assessing the competitive picture, the most useful evidence will be verified production milestones, sustained yields and ramp rates, customer adoption, packaging capacity, and costs—not node names or capital announcements in isolation. TSMC’s roadmap is ambitious; its leadership and financial benefits remain dependent on execution.
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