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Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →TSMC unveiled its A14 process on April 23, 2025—not a finished chip, but a future 1.4nm-class manufacturing technology. The company says A14 combines second-generation nanosheet gate-all-around (GAA) transistors with its NanoFlex Pro standard-cell platform to deliver, versus N2, up to 15% higher speed at the same power, up to 30% lower power at the same speed, and more than 20% higher logic density. TSMC’s current roadmap still targets volume production in 2028.
Those figures are company projections, not independent silicon benchmarks. A14 is not shipping today, and “1.4nm” is a node-generation label—not a literal measurement of every transistor feature.
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What TSMC actually unveiled
At its 2025 North America Technology Symposium, TSMC introduced A14, its next-generation logic process. The formal name is A14; “1.4nm” is the commonly used class description.
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TSMC positions A14 for high-performance computing, artificial intelligence, client computing, smartphones, and other advanced logic products. The company’s current technology page says development is progressing well and volume production is planned for 2028. That makes A14 a roadmap technology rather than a process used in currently available CPUs, GPUs, phones, or accelerators.
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The announcement matters because advanced process nodes influence how much computing manufacturers can fit into a given area and how much power that computing requires. However, the final benefit depends on the chip’s architecture, design libraries, packaging, memory system, cooling, and manufacturing economics.
TSMC’s announcement introduced the transistor and design technologies, while its current A14 technology page provides the latest public roadmap status.
What “1.4nm” means—and does not mean
Modern process names such as 5nm, 3nm, 2nm, and 1.4nm are best understood as technology-generation labels. They no longer correspond to one universally defined physical dimension shared by every transistor feature.
Calling A14 “1.4nm” does not mean every part of each transistor measures 1.4nm. It also does not mean an A14 transistor is simply one-tenth the size of a transistor from a 14nm process. Node names alone cannot determine a chip’s speed, power consumption, density, wafer cost, or retail price.
For precision, this article uses TSMC’s official name, A14, and treats “1.4nm-class” as shorthand for its position in the company’s process roadmap.
Second-generation GAA nanosheet transistors
A14 advances TSMC’s nanosheet, or gate-all-around, transistor technology. Earlier advanced TSMC nodes such as N3 used FinFETs. TSMC’s N2 process introduced the company’s first nanosheet/GAA generation, while A14 is described as the second generation.
In a FinFET, the gate wraps around three sides of a raised channel, or fin. In a GAA transistor, the gate surrounds the channel more completely. A nanosheet design uses horizontally stacked semiconductor sheets as the conducting channels.
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The more complete gate control can help manage leakage and maintain control of the channel as dimensions shrink. But “second generation” does not necessarily mean an entirely new transistor concept. It describes TSMC’s process-generation progression and includes improvements in transistor construction, manufacturing, design rules, libraries, and design-technology co-optimization.
That distinction is important: the transistor structure is one part of A14, while the surrounding process and design ecosystem determines how much of its potential a real product can use.
What TSMC means by a “full-node” advantage
TSMC describes A14 as a full-node improvement over N2. In practical terms, that means the company is presenting a combined advance in performance, power efficiency, and logic density rather than a small refinement to an existing process.
“Full node” is TSMC’s characterization, not a universally standardized industry measurement. It should not be interpreted as a promise that every A14 chip will improve by the same percentage in every category.
TSMC’s claimed A14 improvements
| Comparison with N2 | TSMC’s stated A14 benefit |
|---|---|
| Speed at the same power | Up to 15% higher |
| Power at the same speed | Up to 30% lower |
| Logic density | More than 20% higher |
| Later public range | 10–15% speed gain, 25–30% power reduction, and roughly 20% chip-density improvement |
TSMC later used more cautious ranges in public material, including a 10–15% speed improvement, 25–30% power reduction, and approximately 20% density improvement. The figures come from TSMC, not independent A14 benchmarks.
The operating points also matter:
- Same power: An A14 design could potentially run faster while using the same power budget as an N2 design.
- Same speed: An A14 design could potentially achieve the same performance while consuming less power.
- Density: More logic may fit into a comparable area.
These figures are alternative comparisons, not additive benefits. A chip cannot automatically claim the maximum speed gain, maximum power reduction, and maximum density increase simultaneously. Results depend on voltage, libraries, clock targets, architecture, thermal limits, and how extensively the customer optimizes the design for A14.
Logic density is also not the same as whole-chip shrinkage. SRAM, analog circuits, I/O, cache, clocking, power delivery, interconnect, and design-rule restrictions may scale differently. A more than 20% logic-density improvement does not mean every finished A14 chip will be 20% smaller.
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TSMC’s published figures are available in its ESG announcement and later customer newsletter material.
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What NanoFlex Pro adds
NanoFlex Pro is not another transistor type. It is TSMC’s updated standard-cell architecture, developed from the company’s NanoFlex approach.
Standard cells are reusable building blocks for digital logic. Their height, transistor arrangement, routing, and power characteristics affect how efficiently a chip’s logic can be implemented. A flexible cell library can let designers choose different trade-offs between speed, power, and area instead of applying one uniform optimization to the entire chip.
NanoFlex Pro therefore works alongside the A14 transistor technology. The GAA nanosheet structure provides the transistor foundation; NanoFlex Pro helps customers turn that foundation into usable circuit designs. This is an example of design-technology co-optimization, or DTCO.
TSMC describes NanoFlex Pro in its A14 announcement and on its NanoFlex technology page.
A14 compared with N2, N2P, and A16
| Node | Role | Key technology | Public timing |
|---|---|---|---|
| N2 | First TSMC nanosheet generation | First-generation GAA/nanosheet transistors | Volume production began in the fourth quarter of 2025 |
| N2P | Enhanced N2-family process | N2 derivative and refinement | Production scheduled for the second half of 2026 |
| A16 | Separate advanced node aimed particularly at data-center products | Nanosheets plus Super Power Rail power delivery | Later roadmap material places production in 2027 |
| A14 | Full-node successor to N2 | Second-generation nanosheet/GAA transistors and NanoFlex Pro | Production planned for 2028 |
N2 is the baseline from which TSMC measures A14’s headline improvements. N2P is an enhanced member of the N2 family, not the same generation as A14.
A16 should also not be treated as simply “A14 before A14.” TSMC announced A16 with nanosheet transistors and Super Power Rail, a power-delivery architecture intended to improve power distribution and free front-side routing resources. Earlier TSMC material targeted A16 for 2026, while later 2026 roadmap material places it in 2027. That change illustrates why roadmap dates should be treated as plans rather than shipping guarantees.
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Relevant roadmap sources include TSMC’s 2nm technology page, its A16 announcement, and the company’s 2026 annual-meeting material.
Does A14 use backside power delivery?
The initial A14 description should not be casually presented as a backside-power process. Available coverage describes A14 as using front-side power delivery, while TSMC has separately associated Super Power Rail or backside-power technology with A16 and later technology families.
Backside power can reduce front-side routing congestion and voltage drop, but it also adds manufacturing complexity. It is not automatically included in every newer process node. TSMC has not, in the cited public material, confirmed that every A14 variant will use backside power.
Does A14 require High-NA EUV?
TSMC has said that A14-class manufacturing does not require High-NA EUV lithography. That means High-NA EUV is not a prerequisite for the announced A14 plan, which could help TSMC manage equipment costs and maintain manufacturing continuity.
It does not mean A14 will be simple or inexpensive to manufacture. TSMC has not publicly disclosed every lithography step, mask strategy, or process-complexity detail. The absence of a High-NA requirement does not eliminate yield risk, multipatterning challenges, wafer cost, or ramp-up difficulty.
Tom’s Hardware’s coverage reports TSMC’s position on High-NA EUV.
What A14 could mean for AI, HPC, phones, and PCs
For AI accelerators and high-performance computing, A14 could potentially provide more compute in a fixed area, lower active power at a target performance level, or higher performance within a fixed thermal envelope. Those benefits are especially valuable where data-center electricity, cooling capacity, and rack density limit system growth.
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- Military-grade components deliver rock-solid power and longer lifespan for ultimate durability
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- 3.125-slot design with massive fin array optimized for airflow from three Axial-tech fans
- Phase-change GPU thermal pad helps ensure optimal thermal performance and longevity, outlasting traditional thermal paste for graphics cards under heavy loads
Client CPUs, phone application processors, and other advanced chips could likewise use the process to balance performance, battery life, heat, and die area. But process scaling is only an enabling technology. It does not by itself solve memory bandwidth, HBM availability, interconnect bottlenecks, advanced-packaging capacity, software efficiency, or cooling.
An A14-based GPU or processor could still be constrained by architecture, memory, packaging, yield, or cost. The process node alone cannot guarantee a faster product or a better consumer experience.
The commercial questions still open
A14’s success will depend on more than its projected PPA—performance, power, and area—metrics.
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- Wafer and transistor cost: A denser process may still have more expensive wafers or greater process complexity.
- Design migration: Customers need mature process-design kits, standard-cell libraries, intellectual property, electronic-design-automation support, and verification flows.
- Power delivery: Front-side delivery may suit some products, while extremely power-dense HPC designs may benefit from more advanced delivery architectures.
- Packaging: Advanced logic can be limited by packaging capacity and HBM supply.
- Customer adoption: TSMC has not publicly identified specific A14 products or customers in the cited sources.
- Manufacturing location: The available material does not establish that every A14 wafer will be made in Taiwan, Arizona, or any other particular location.
There are also no publicly cited independent A14 silicon benchmarks in the supplied sources. Until customer designs and production data emerge, TSMC’s projections should be read as targets and technical claims rather than verified product results.
Is TSMC’s 2028 target credible?
It is a current company roadmap target, not a confirmed commercial launch date. As of August 18, 2026, TSMC’s public position was that A14 development was progressing well and volume production remained scheduled for 2028.
The cited TSMC material does not establish a precise quarter. Reports that specify the first or second half of 2028 should therefore be attributed separately and should not be presented as confirmed TSMC guidance. Production targets can also refer to the start of volume manufacturing rather than the immediate availability of large numbers of consumer products.
Bottom line
TSMC’s A14 is a real, announced future process—not a currently shipping chip. It combines second-generation GAA nanosheet transistors with NanoFlex Pro design technology and is intended to provide a full-node improvement over N2. TSMC projects up to 15% more speed at the same power, up to 30% lower power at the same speed, and more than 20% higher logic density, while later material gives somewhat narrower ranges.
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