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Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Short answer: The Biden administration announced a funding opportunity of up to approximately $285 million in May 2024 for a semiconductor research institute focused on digital twins. The proposal later became a finalized $285 million federal award to the Semiconductor Research Corporation Manufacturing Consortium Corporation on January 3, 2025. The resulting institute, called SMART USA, is headquartered in Durham, North Carolina.
The award is part of a broader public-private investment of more than $1 billion. It is research and development funding—not a direct payment to a chipmaker building a factory—and its stated benefits remain five-year targets rather than proven results.
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At a glance
| Item | Details |
|---|---|
| Institute | SMART USA, or Semiconductor Manufacturing and Advanced Research with Twins USA |
| Federal award | $285 million |
| Recipient and operator | Semiconductor Research Corporation Manufacturing Consortium Corporation |
| Headquarters | Durham, North Carolina |
| Focus | Digital twins for semiconductor design, manufacturing, packaging, assembly and testing |
| Final award announcement | January 3, 2025 |
| Broader investment | More than $1 billion, according to Commerce |
Commerce announced the finalized award on January 3, 2025.
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On May 6, 2024, the Commerce Department issued a Notice of Funding Opportunity seeking proposals for a new Manufacturing USA institute. The announcement said CHIPS for America anticipated investing up to approximately $285 million in an institute devoted to semiconductor digital twins.
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That was not yet a payment to a company or a grant for constructing a semiconductor fabrication plant. The proposed funding covered institute operations, basic and applied research, shared physical and digital facilities, demonstrations, and workforce training. The work was intended to span semiconductor design, fabrication, advanced packaging, assembly and testing.
Commerce later said three teams had been invited to submit full applications. On November 19, 2024, it announced proposed negotiations with SRC. The final award followed in January 2025.
That progression matters when reading older headlines: the May announcement was a funding opportunity, while the January announcement described a finalized award.
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What is a semiconductor digital twin?
A digital twin is a virtual model representing the structure, context and behavior of a physical object, process or system. In semiconductor manufacturing, the model could represent:
- A chip or package design
- A fabrication or packaging process
- An individual manufacturing tool
- A production line or factory
- A facility upgrade
- Part of the wider semiconductor supply chain
It is more than a static 3D image or virtual-reality replica. A useful twin connects models with real-world data so engineers can simulate changes, monitor performance, validate assumptions and optimize operations before making expensive physical changes.
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The National Institute of Standards and Technology describes the program as supporting digital-twin research across semiconductor design and manufacturing. Depending on the application, a twin might combine equipment data, sensor readings, process models, manufacturing software and engineering simulations.
Why could digital twins help chip manufacturers?
Semiconductor production is expensive, highly interconnected and sensitive to small changes in materials, temperatures, chemicals, timing and equipment settings. Physical experiments can consume time, wafers, machine capacity and engineering resources.
A reliable digital twin could help organizations:
- Plan production capacity and factory changes
- Test process adjustments virtually before deployment
- Identify potential problems earlier in development
- Optimize production and facility operations
- Validate designs and manufacturing changes
- Coordinate research among companies, universities and laboratories in different locations
- Use artificial intelligence and other tools to analyze complex manufacturing data
The important qualification is that these are intended uses and program objectives. The award does not establish that SMART USA has already reduced chip costs, shortened development cycles or improved factory yields.
Is this manufacturing money under the CHIPS Act?
It is CHIPS Act funding, but it is not the same as a direct manufacturing incentive for building or expanding a fab.
CHIPS for America has separate functions. The CHIPS Program Office administers manufacturing incentives, while the CHIPS Research and Development Office, within Commerce and NIST, administers research programs. The SMART USA award came through the research and development side.
In practical terms, the money supports shared research infrastructure, demonstrations and training rather than directly financing a company’s new production facility. NIST provides additional context on the CHIPS research and development programs.
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Commerce awarded the money to the Semiconductor Research Corporation Manufacturing Consortium Corporation, commonly associated with the Semiconductor Research Corporation, or SRC. SRC is expected to establish and operate SMART USA from Durham, North Carolina.
Commerce said the institute would bring together semiconductor companies, startups, universities, national laboratories, manufacturing organizations, workforce groups and other supply-chain participants. Its January 2025 announcement described planned participation spanning more than 30 states and more than 150 expected partner entities, including 10 national laboratories, five Manufacturing USA institutes, five economic-development agencies, and four trade and union groups.
Those figures describe planned or expected participation as reported by Commerce; they should not be interpreted as an independently audited membership count.
What will the institute pay for?
The program is designed around a shared environment where industry and research organizations can work with both physical and digital resources. Its activities are expected to include:
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- Research into semiconductor digital-twin methods
- Shared physical and digital facilities
- Industry-relevant demonstrations
- Tools for design, process, equipment and factory modeling
- Workforce education and training
- Collaboration across fabrication, packaging, assembly and testing
This design reflects a broader technology-policy approach: domestic semiconductor competitiveness depends not only on physical fabs, but also on engineering software, process data, measurement systems, advanced packaging, workforce skills and research infrastructure.
SMART USA’s five-year targets
Commerce’s January 2025 announcement listed the institute’s goals for its first five years:
- Reduce U.S. chip-development and manufacturing costs by more than 40%
- Reduce development cycle times by 35%
- Reduce semiconductor-manufacturing greenhouse-gas emissions by 30%
- Train and educate more than 110,000 workers and students
- Address shared digital-twin challenges across design, manufacturing, advanced packaging, assembly and test
These are targets, not completed outcomes. They should not be presented as savings or emissions reductions already achieved.
How much money is involved?
The amount changed in status over time:
- May 6, 2024: Commerce announced a funding opportunity of up to approximately $285 million.
- November 19, 2024: Commerce announced a proposed award and negotiations with SRC.
- January 3, 2025: Commerce announced the finalized $285 million award.
Commerce also described the program as part of a combined public-private investment of more than $1 billion. Therefore, $285 million is the federal award—not the total cost of the institute or the total value of all participating investments.
What could limit the program’s results?
Building a useful semiconductor digital twin is difficult. It requires more than simulation software or visual models. Potential challenges include:
- Data quality: Sensors may be delayed, inconsistent or poorly calibrated.
- Model accuracy: A model can become stale when equipment, materials or recipes change.
- Interoperability: Different vendors’ systems may not exchange data cleanly.
- Intellectual property: Manufacturers may be reluctant to share recipes, defect data or equipment performance information.
- Validation: A model must be checked against physical production results.
- Scale: A demonstration that works in a laboratory may fail under production-volume conditions.
- Cybersecurity: Collaborative cloud systems create security, export-control and supply-chain risks.
- Optimization trade-offs: Improving one metric could harm yield, reliability, energy use or equipment life.
- Workforce adoption: Training has less value if the resulting tools are not widely used.
There are also technical trade-offs. A highly detailed model may be too slow for real-time decisions, while a simpler model may be faster but less accurate. Artificial intelligence can improve prediction, but manufacturers may still need explainable recommendations before acting on high-cost process changes.
Why the investment matters
For U.S. semiconductor policy, SMART USA combines three priorities: domestic manufacturing capacity, shared research infrastructure and workforce development. It also recognizes that advanced chip production depends on software and data systems as well as physical factories.
The potential benefit is long term. Digital twins could help researchers and manufacturers experiment more efficiently, but they cannot eliminate physical testing or guarantee lower consumer prices. Any effect on products such as phones, computers or vehicles would likely depend on whether the research produces tools that work reliably across commercial production environments.
For now, the most accurate description is: the administration proposed the funding in May 2024, Commerce selected SRC for negotiations in November, and Commerce finalized the $285 million award to SMART USA in January 2025.
Quick Recap
Sources
- Commerce: May 2024 digital-twin funding opportunity
- Commerce: November 2024 proposed award
- Commerce: January 2025 finalized award
- NIST: digital-twin program description
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