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SMIC did put a near-5nm-class chip into a commercial Huawei phone: TechInsights identified the Kirin 9030, launched in late 2025, as made on SMIC’s N+3 process. But that is not evidence that SMIC has matched TSMC or Samsung on 5nm density, yield, cost or production scale. N+3 is a scaled evolution of SMIC’s 7nm-class technology, made without EUV and with important economic and manufacturing limits still unresolved.
What was achieved—and what was not
The 2025 claim is partly validated, but the wording matters. Independent teardown analysis identified a shipping Huawei processor made on SMIC N+3, a process TechInsights described as approaching 5nm-equivalent capability. TechInsights also said N+3 remains significantly less scaled than leading commercial 5nm processes from TSMC and Samsung. TechInsights’ Kirin 9030 analysis is the key evidence: it examines a physical product, rather than relying on a roadmap or an unverified production claim.
That makes the achievement real at the smartphone-product level. It does not establish that SMIC can make equivalent chips at comparable cost, with comparable yields, or in volumes sufficient to serve a broad market. “Commercially available” is not the same as proven, high-volume, economically competitive production.
What N+3 and “5nm” mean
Process-node labels such as 5nm are generation names, not universal measurements of one physical feature. Comparing two processes requires looking at characteristics such as transistor and wiring density, power, performance, and design rules—not just the number in the name.
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TechInsights calls N+3 a scaled evolution of SMIC’s 7nm-class technology. It is best described as near-5nm-class or 5nm-equivalent in certain respects, not as a direct match for TSMC’s or Samsung’s 5nm processes. N+2 is associated with an earlier SMIC 7nm-class generation; N+3 adds further scaling and refinements. The name alone does not establish a standardized node or parity with another foundry.
How SMIC made advanced silicon without EUV
Leading-edge manufacturing uses extreme ultraviolet (EUV) lithography on critical layers of advanced processes. SMIC instead relies on 193nm deep ultraviolet (DUV) immersion lithography and repeated patterning to form features that require fewer steps with EUV. This is a technically demanding workaround, not proof that lithography equipment no longer matters.
Multi-patterning divides pattern formation into additional exposures and process steps. That can extend the capabilities of available DUV equipment, but it increases process complexity and the risk of alignment errors. The likely trade-offs are longer production cycles, lower throughput, and pressure on yield and wafer cost. A 2025 congressional witness described SMIC and Huawei’s effort to scale a 5nm-class process without EUV through DUV-based multi-patterning. ASML’s 2025 annual report says EUV systems and certain advanced DUV immersion systems are subject to export licensing restrictions. Congressional testimony on the effort and ASML’s 2025 annual report provide the equipment-policy context.
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What the evidence says about yield, cost and scale
Public information confirms a real N+3 smartphone product, but does not disclose SMIC’s N+3 wafer-start capacity, stable yields, cost per good die, or the share of wafers meeting customer specifications. It also does not establish whether the process is broadly available to customers beyond Huawei. Those gaps prevent a confident claim that N+3 is mature, high-volume production on the terms readers often associate with “mass production.”
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Yield reports are especially uncertain. CSIS summarized conflicting industry-source estimates: one report put yield for an advanced Huawei AI chip near 40%, while other sources cited by CSIS put it closer to 20%. These are not audited company-wide N+3 figures and should not be treated as settled measurements. Yield can also mean different things:
- Wafer yield: the share of dies that pass wafer-level testing.
- Packaged yield: the share that remain usable after assembly and testing.
- Effective yield: the share that meet a particular performance or power bin.
- Economic yield: whether usable chips can be produced at a cost that makes the process competitive.
These distinctions matter because a working chip does not reveal the number of failed dies or the cost of producing each usable one. CSIS’s discussion of disputed yield estimates summarizes the uncertainty.
Why a smartphone chip does not prove AI-chip parity
A smartphone processor demonstrates that N+3 can support a sophisticated mobile design. It does not show that the same process can economically make much larger data-center accelerators. Larger dies are more exposed to defects: even if defects are relatively uncommon, a bigger chip has more area in which one can make a die unusable.
AI accelerators also bring demanding performance and power targets, extensive wiring, and complex memory and packaging requirements. Defects become more costly when they affect a large, valuable die. TechInsights concluded that N+3 could produce a production-quality smartphone processor but was not a viable solution for large data-center AI chips, citing DUV limitations, process immaturity and expected yield problems on larger dies. TechInsights’ assessment of N+3 for AI chips draws this distinction directly.
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Earlier 2025 reporting raised reasonable doubts about whether a newer process was ready for broad use. A Reuters report on Huawei’s MateBook Fold found that its chip used SMIC’s older N+2 process, not N+3. That was a time-specific indication that the newer process was not yet evident in that product; it did not prove that SMIC would never produce N+3 silicon. The MateBook Fold report should be read in that context.
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On December 11, 2025, TechInsights identified the Kirin 9030 in Huawei’s Mate 80 series as an N+3 chip. Later TechInsights analysis also identified the Kirin 9030 Pro as fabricated on N+3 and examined its packaging. The later teardown evidence changed the answer from “not demonstrated in a shipping product” to “demonstrated for mobile silicon,” without resolving scale or economics. TechInsights’ Kirin 9030 Pro analysis and its packaging analysis add detail.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What this means for Huawei and China’s chip industry
Huawei is the most visible customer and test case. The strategic significance is that Huawei can combine its own chip design with SMIC fabrication, Chinese packaging, and a domestic device ecosystem. That combination can support useful products even if the underlying manufacturing process is less efficient than foreign alternatives. TechInsights identified the Kirin 9030 Pro as a 9-core, 14-thread processor made on N+3 and packaged in China; those specifications describe that chip, not the process’s general competitiveness.
Export controls are a major constraint, but the outcome is not binary. They limit access to EUV and certain DUV equipment, among other manufacturing inputs. SMIC’s workaround shows that restrictions have not prevented every advanced-chip achievement; it does not show that the restrictions have no effect. Extra process complexity may sustain domestic capability while worsening production economics and limiting the products or volumes that are practical.
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How to judge the next “5nm” claim
A node label is only one part of the story. For future announcements, look for evidence that separates a technical demonstration from a competitive manufacturing business:
- Independent teardown evidence identifying the process in a shipping product.
- Comparable data on chip density, power and performance—not just a node name.
- More products using N+3, including evidence beyond Huawei.
- Disclosure or credible independent estimates of capacity, yield, shipment volume and cost per good die.
- Evidence that the process can support larger chips, such as AI accelerators, without unacceptable yield or power penalties.
- Signs of improved throughput, lower defect rates, or broader deployment of domestic lithography equipment.
Until those measures are available, the strongest conclusion is limited but meaningful: SMIC has demonstrated near-5nm-class mobile silicon under equipment constraints, while public evidence does not establish leading-foundry parity or economical large-scale production.
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