PowerLattice announced a $25 million Series A on November 17, 2025, to develop power-delivery chiplets for AI processors and other high-performance chips. Playground Global and Celesta Capital jointly led the round. Former Intel CEO Pat Gelsinger is a Playground Global general partner and a PowerLattice board member. The company says its technology can reduce compute power needs by more than 50%, but the available sources do not provide independent benchmarks or named production customers to verify that claim.
What PowerLattice announced
PowerLattice, a semiconductor startup founded in 2023 and headquartered in Vancouver, Washington, emerged from stealth on November 17, 2025. Its announcement described a $25 million Series A jointly led by Playground Global and Celesta Capital, bringing the company’s reported total funding to $31 million. The company also lists operations in Chandler, Arizona. PowerLattice’s announcement describes its focus as power delivery for AI accelerators and data-center processors.
The round is a financing event, not proof that the company’s hardware has achieved commercial adoption. The announcement and subsequent reporting do not establish the round’s valuation, investor-by-investor ownership, or how much Gelsinger may have invested personally.
What the company is building
PowerLattice is developing a power-management chiplet, not an additional compute chiplet. In broad terms, voltage regulators convert and control electricity before it reaches a processor. PowerLattice’s approach is to put power regulation directly in, or very close to, the processor package, shortening the path between power conversion and the compute die. The company says its architecture tightly couples power and compute and can adapt to different system-on-chip power topologies. Its website describes the product as a power-delivery chiplet for high-performance processors.
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The proposed benefit is reduced loss and faster response as a processor’s power demand changes. The idea is relevant to GPUs, CPUs, AI accelerators, and custom data-center processors, where workloads can shift rapidly. It addresses one part of the power-delivery chain; it does not by itself generate electricity, remove the need for cooling, or resolve the broader constraints of data-center infrastructure.
Why power delivery matters in AI data centers
High-performance processors need substantial, carefully regulated electrical power. Electricity must travel through a sequence of power supplies, boards, package connections, and regulation stages before it reaches the circuitry doing the computation. Losses along that route mean some input power does not become useful computing work. Power delivery also affects how quickly a system can respond to changing loads, and poor power conditions can contribute to throttling or reliability concerns.
Moving regulation closer to a processor could reduce some distribution losses and help a system use its available power budget more effectively. If that works at system scale, it could support more compute within a fixed rack-power limit. But the actual effect depends on the processor, package, workload, regulator behavior, and cooling design. A component-level efficiency gain should not be read as an equivalent reduction in a data center’s total electricity use.
How large are PowerLattice’s performance claims?
PowerLattice says its approach can cut compute power requirements by more than 50%. Its website also claims a potential two-to-three-times improvement in performance per watt, along with reduced power noise, less power-related throttling, greater compute utilization, longer system lifetime, and more computation per rack. These are company claims, not independently verified results in the available coverage.
The sources reviewed do not give a complete test methodology, baseline hardware, workload definitions, chiplet area or thermal data, or efficiency results across voltage and frequency ranges. They also do not provide independent laboratory validation or a peer-reviewed paper. Without those details, it is not possible to tell whether the power figure refers to regulator losses, package-level power delivery, total processor power, or a wider system boundary—or whether the performance-per-watt comparison holds for particular workloads.
What stage is the hardware at?
There are meaningful early-stage milestones, but they should not be confused with production readiness. PowerLattice said it had initial silicon in hand and was developing engineering samples for processors rated above one kilowatt. TechCrunch reported that TSMC was producing an initial batch of chiplets and that an unnamed manufacturer was testing their functionality. The report said the company planned to make the product available for testing by additional customers in the first half of 2026; a plan to begin testing is not evidence that testing was completed or that a customer qualified the product. TechCrunch’s report does not name the manufacturer or a production customer.
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The distinction between development stages matters:
- Silicon exists: PowerLattice said it had initial silicon.
- Samples are being developed: the company said engineering samples were in progress for 1-kilowatt-plus processors.
- Functionality is being tested: TechCrunch reported testing by an unnamed manufacturer.
- Qualification or a production design win: not established in the available sources.
- Volume shipments: not established in the available sources.
Pat Gelsinger’s role—and what it does not prove
Gelsinger was Intel’s CEO from 2021 until December 2024, according to GeekWire’s funding coverage. He is now a general partner at Playground Global and is listed on PowerLattice’s board, according to the company’s leadership page. His background gives the financing announcement added visibility in the semiconductor industry.
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That connection does not establish that Gelsinger personally supplied a specific amount of the financing, nor does a prominent board member independently validate the technology. The confirmed lead investors are Playground Global and Celesta Capital.
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Who founded PowerLattice?
PowerLattice identifies three founders in its announcement: Dr. Peng Zou, CEO and president; Gang Ren, head of engineering; and Sujith Dermal, head of systems and applications. The company says the team’s experience spans integrated magnetics, analog integrated circuits, power management, and system design, with work across companies including Qualcomm, NUVIA, Intel, Huawei, Dialog, and Freescale. Those affiliations provide career context, but do not by themselves establish who was responsible for any particular prior product. The company announcement names the founders and describes their backgrounds.
Who might buy the chiplet?
The potential market includes designers of GPUs, CPUs, AI accelerators, and custom data-center processors. TechCrunch identified companies such as Nvidia, AMD, and Broadcom as part of the broader potential customer universe, alongside specialized AI-chip developers. That is market context, not evidence of adoption: the available sources do not establish that Nvidia, AMD, Broadcom, Cerberus, Grok, d-Matrix, NextSilicon, or another named chipmaker has ordered or adopted PowerLattice products.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Competition and the adoption hurdle
TechCrunch identified Empower Semiconductor as a close competitor and reported that it raised a $140 million Series D in September 2025. The comparison is not simply about which company has a smaller regulator. Processor designers would need to assess where each solution places voltage regulation, how it performs under changing workloads, how it connects to the package, and what it takes to manufacture and qualify at scale.
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For a power chiplet, commercial success depends on more than a working sample. Customers would need to weigh potential energy and performance benefits against package redesign, advanced-packaging availability, added supplier dependence, reliability and yield testing, and total cost. A solution that improves chip-level efficiency may produce a smaller gain at the data-center level, and the savings may vary by workload and system design. Processor companies may also prefer in-house power-delivery approaches.
A practical evaluation would need answers to questions such as:
- What baseline and system boundary are used for the claimed power reduction?
- Are comparisons made at equal throughput, equal clock speed, or equal power?
- How does the chiplet behave under transient AI workloads, and what are its thermal and electromagnetic-interference characteristics?
- What package changes, manufacturing process, yield effects, and reliability testing are required?
- What are the chiplet’s cost and bill-of-materials impact, and does it require software or firmware changes?
PowerLattice calls its product the “industry’s first power delivery chiplet,” but that is the company’s positioning, not an independently established finding. It also says it is not affiliated with Lattice Semiconductor Corporation; the clarification appears on its About page.
What the funding means for readers
The $25 million round gives PowerLattice capital to advance a specialized hardware product aimed at a real engineering challenge. The company has reported silicon, sample development, and manufacturer testing, while its efficiency figures remain unverified in the available sources. For investors, technology buyers, and data-center operators, the key milestones to watch are reproducible performance results, customer qualification, production economics, and volume availability—not the funding announcement alone.
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