Intel is collaborating with SAIMEMORY, a Tokyo-based SoftBank Corp. subsidiary, on Z-Angle Memory (ZAM), a proposed stacked-DRAM architecture for artificial-intelligence and high-performance-computing systems. The project is targeting prototypes in 2027 and commercialization by 2030. It is not yet a shipping product, a consumer memory upgrade, or a revival of Intel Optane.
The technology could eventually compete with high-bandwidth memory (HBM), but Intel and SAIMEMORY have not published product-level figures for capacity, bandwidth, latency, power, package design, pricing, or customer support.
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What Intel and SoftBank actually announced
The partnership announced on February 2, 2026, is between Intel and SAIMEMORY, not a conventional memory-product venture directly operated by SoftBank’s parent company. SAIMEMORY is a subsidiary of SoftBank Corp. Intel describes the effort as the Z-Angle Memory program, or ZAM.
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsIntel says it will contribute technology collaboration, innovation, intellectual property, and standards work. The company is also bringing research from its U.S. Department of Energy Advanced Memory Technology program and its Next Generation DRAM Bonding initiative. SAIMEMORY is expected to contribute technology and innovation and lead commercialization.
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The stated goal is a memory architecture with greater density and bandwidth, lower latency and power consumption, and better packaging economics for AI and HPC systems. Those are development objectives, not published product specifications or independently verified performance results. Intel’s announcement provides the project’s current public description.
What ZAM is—and what it is not
Intel’s precise description is a stacked DRAM architecture. That suggests ZAM is primarily an architecture, bonding, and packaging approach for assembling DRAM, rather than a wholly new memory-cell chemistry.
The name stands for Z-Angle Memory, but the public announcements do not explain the “Z-angle” in enough engineering detail to establish how the design works. Intel and SAIMEMORY have not disclosed the layer count, interface, package dimensions, signaling method, process technology, capacity per package, bandwidth, latency, thermal characteristics, or power figures.
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Why AI systems need new memory approaches
Modern AI accelerators repeatedly move model weights, activations, and intermediate data between compute engines and memory. As models and accelerator clusters grow, memory can become a limiting factor even when the processors themselves are powerful enough.
- Bandwidth: More bandwidth helps deliver data to GPUs, CPUs, and other accelerators without leaving compute resources idle.
- Capacity: More local memory can reduce movement between fast memory, slower memory tiers, and storage.
- Latency: Faster access can improve responsiveness for workloads that cannot hide memory delays.
- Power: Memory transfers consume energy, making efficiency important in large data centers.
- Packaging: Shorter, denser interconnects can help integrate memory closely with the accelerator.
Intel says conventional memory architectures are not keeping pace with AI and HPC requirements. ZAM is intended to address those bottlenecks, although the company has not shown public system-level benchmarks proving that it does so in a production-ready design.
ZAM versus HBM
ZAM is being developed for a similar broad purpose as HBM: supplying very high-bandwidth memory close to an AI or HPC accelerator. Network World described the proposed technology as a potential HBM competitor, noting similarities between the concepts. That is useful market context, but it is not evidence that ZAM uses HBM’s interface, package structure, standards, performance envelope, or manufacturing process.
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The most accurate description is that ZAM is an intended alternative or competing approach to HBM-class memory. Whether it can match or exceed HBM will depend on prototype results, manufacturing yields, power behavior, ecosystem support, and cost.
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| Area | Conventional DRAM | HBM | ZAM |
|---|---|---|---|
| Basic description | Mainstream system memory | Commercial high-bandwidth stacked memory | Proposed next-generation stacked DRAM architecture |
| Primary target | General computing | AI, GPUs, and HPC accelerators | AI and HPC systems |
| Availability | Established | Established commercial technology | Development stage |
| Public performance data | Widely available by product | Widely available by product | Not disclosed in the cited announcements |
| Timing | Available now | Available now | Prototypes targeted for 2027; commercialization targeted for 2030 |
| Main uncertainty | System bandwidth and latency | Cost, supply, and packaging complexity | Technical validation, manufacturability, and ecosystem adoption |
How ZAM differs from Optane
Intel’s involvement naturally recalls Optane, the company’s former persistent-memory and storage technology based on 3D XPoint. But the two efforts belong to different categories.
- Optane: Persistent memory and storage technology designed to retain data without power.
- ZAM: Proposed stacked DRAM architecture intended to improve bandwidth, density, power, and integration for AI and HPC.
The public announcements do not describe ZAM as Optane-based, persistent, or a continuation of the Optane product line. Calling this a strategic return to memory development is reasonable; calling it an Optane relaunch is not.
Where the project came from
Intel says ZAM builds on work from the U.S. Department of Energy’s Advanced Memory Technology research program and its Next Generation DRAM Bonding initiative. The AMT work was managed through Sandia National Laboratories, Lawrence Livermore National Laboratory, and Los Alamos National Laboratory, according to Intel.
Intel also says its AMT-funded work produced proof points and performance validation for the stacked-DRAM concept, while NGDB demonstrated higher DRAM density and bandwidth with lower latency and energy consumption. Those statements come from Intel; the cited material does not provide a full independent technical paper or benchmark dataset for ZAM.
What the NEDO funding means
On April 21, 2026, Intel and SAIMEMORY said their joint proposal had been selected for a 3.5-year NEDO-funded Japanese research and development program. The program focuses on manufacturing technology for high-density, wide-bandwidth, low-power memory.
The award is meaningful because it gives the project additional institutional and development support and indicates movement beyond the initial partnership announcement. It does not prove that a prototype has been completed, that production is ready, or that customers have committed to using ZAM. It also does not guarantee the 2030 commercialization target.
Read the April NEDO update from Intel for the company’s description of the program.
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Timeline: announcement, prototypes, and commercialization
- February 2, 2026: Intel announced its collaboration with SAIMEMORY.
- First quarter of 2026: The companies targeted the start of operations. The announcement does not independently confirm completion of that milestone.
- 2027: Prototypes are targeted. This is not a commercial availability date.
- April 21, 2026: Intel and SAIMEMORY announced selection for the NEDO-backed development program.
- Three and a half years: The stated duration of the NEDO research and development program.
- 2030: Commercialization is targeted. This is a goal, not a guaranteed launch.
What remains unknown
The announcements do not establish:
- bandwidth per package or per system;
- memory capacity;
- latency figures;
- stack height or layer count;
- power consumption;
- interface and standards compliance;
- manufacturing process or production location;
- named DRAM, packaging, substrate, or accelerator partners;
- pricing or cost relative to HBM;
- customer commitments;
- compatibility with existing servers, GPUs, or AI accelerators.
Intel mentions standards collaboration, but no finished interface standard or ecosystem certification has been identified in the cited material.
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The main technical and commercial risks
Stacking can increase density and bandwidth, but it can also make manufacturing more difficult. Bonding quality, yield, thermal management, package reliability, and testing all become important. A successful laboratory or prototype demonstration does not automatically translate into high-volume production.
Power claims also require context. Lower memory power could improve efficiency, but it would not necessarily lower total accelerator or data-center power if the system consumes more energy elsewhere. Likewise, higher bandwidth does not guarantee lower latency or greater usable capacity.
Commercially, ZAM would face an established HBM ecosystem with suppliers, accelerator support, packaging capacity, and customer experience. By 2030, HBM itself may have advanced, while other approaches—including advanced packaging and memory-tier technologies—could change the competitive landscape. Customers may prefer a proven memory technology even if ZAM appears more efficient on paper.
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There is no identified ZAM module, price, retail channel, server qualification, or deployment option today. It is aimed at specialized AI and HPC infrastructure, not ordinary desktop PCs or a direct consumer RAM replacement.
For data-center operators, the project is a technology-development signal rather than a procurement option. Any practical decision would require later evidence on performance per watt, usable capacity, software and accelerator compatibility, production volume, reliability, and total system cost.
For investors and technology watchers, the significant question is not simply whether Intel has announced a new memory name. It is whether Intel and SAIMEMORY can move from a promising stacked-DRAM concept to repeatable manufacturing and a supported ecosystem before HBM and competing technologies advance further.
As of August 18, 2026, no verified source cited here reports a shipping ZAM product, public production specifications, pricing, or independently measured prototype performance.
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