AI chipmakers do not choose a foundry by process-node headline alone. They select a manufacturing system that can co-design logic wafers, high-bandwidth memory (HBM) stacks, interconnects, package assembly, design tools, qualified capacity and a production schedule.
The practical decision is therefore a gated sourcing exercise: define the package and HBM configuration, confirm that the foundry’s process and design ecosystem can implement it, verify qualification and capacity for the required ramp, then compare total cost, yield and supply risk with evidence specific to the chip.
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Why advanced packaging changes the foundry decision
Modern AI accelerators often place several compute dies and multiple HBM stacks in one package. The package is not merely the last assembly step; its interposer, bridge or vertical-stacking scheme determines how much bandwidth can reach the compute dies, how power and heat are managed, and how the design is partitioned across dies.
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TSMC describes CoWoS as a 2.5D technology for high-performance computing (HPC) and AI that integrates multiple system-on-chip (SoC) dies with HBM stacks. Its product description says CoWoS-R connects the SoC and/or HBM through a redistribution-layer (RDL) interposer and has been in volume production since 2023. Those are TSMC’s published claims, not an independent ranking of suppliers. TSMC CoWoS technology page
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Because the package carries the high-speed links between logic and memory, a chipmaker must choose wafer fabrication and packaging together. A foundry with an attractive logic node is not a viable choice if its package design rules, HBM interfaces, assembly yield or delivery schedule cannot support the product’s target.
The selection process, from architecture to production
1. Freeze the system requirements
The chip team first converts workload and system goals into package-level requirements:
- Number, generation and physical arrangement of HBM stacks.
- Required memory bandwidth, capacity, signaling rate and power envelope.
- Compute-die count, die sizes, reticle constraints and whether chiplets are needed.
- Thermal limits, package dimensions, substrate needs and board-level interfaces.
- Target production date, annual volume and acceptable ramp profile.
At this stage, the team should record which requirements are hard limits and which can trade off. For example, reducing HBM stacks may lower package complexity but also reduce bandwidth and capacity. Splitting a large die into chiplets can improve reticle fit or reuse, yet it adds die-to-die links and more assembly and test steps.
2. Match the package architecture
The next gate is architectural fit. The buyer compares 2.5D interposer designs, bridge-based integration and 3D stacking against the specific die and memory arrangement.
| Approach | How logic and HBM are connected | What to verify |
|---|---|---|
| 2.5D interposer | Logic dies and HBM sit side by side on an interposer. TSMC describes CoWoS-R using an RDL interposer for SoC and/or HBM connections. | Interposer size, routing density, reticle limits, HBM interface support, assembly yield and thermal design. |
| Bridge-based integration | A silicon bridge embedded in the package substrate links adjacent dies. Intel describes EMIB as a bridge approach and EMIB-T as adding bridge channels for power delivery and routing needs associated with newer HBM technologies. | Bridge placement, channel count, substrate rules, power delivery, test coverage and supported HBM generations. |
| 3D stacking | Dies are placed vertically with fine-pitch bonding or another stacking method. Intel describes Foveros stacking; TSMC describes SoIC stacking; Samsung describes development of bumpless hybrid copper bonding. | Bonding pitch, thermal path, known-good-die strategy, repairability, stacking yield and design-tool maturity. |
The descriptions in this table come from the vendors’ own technical materials. They establish the types of integration offered, not a neutral performance, cost or yield comparison.
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3. Confirm HBM compatibility and supply
HBM is a separate supply-chain dependency inside the package. A foundry may provide the package process while one or more memory companies provide the HBM stacks. The chipmaker must align the exact HBM generation, stack height, interface, electrical specifications and qualification status with the package design.
Ask each candidate to document which HBM configurations are supported in the proposed package, which memory suppliers and part numbers have completed qualification, and how substitutions would be handled. Public technology pages generally do not disclose customer-specific allocations or guaranteed quantities, so an announcement that a supplier supports HBM does not prove that capacity is reserved for a particular accelerator.
4. Check logic-process and design fit
The logic wafer process must support the die partition, library requirements, power targets and design rules of the accelerator. Equally important are the package-aware design kits, physical-verification rules, signal-integrity models, thermal models, test collateral and intellectual-property blocks needed to close the design.
TSMC presents its HPC platform as a combination of wafer technology, the Open Innovation Platform design ecosystem and 3DFabric packaging. This integrated operating model can reduce the number of interfaces a chipmaker must coordinate, but the buyer still has to confirm that the specific node, package option and EDA/IP versions are released for its schedule. TSMC HPC Platform – 3DFabric
5. Separate demonstrated production from roadmap promises
Production maturity should be recorded with precise status labels:
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- Volume production reported: the supplier publicly states that the process is in volume production.
- Qualification or certification: a process or package has passed a defined technical gate but may not yet be shipping at the required volume.
- Development: the technology is being engineered or demonstrated.
- Planned ramp: the supplier gives a future target that still requires execution and customer qualification.
For example, TSMC’s 2025 annual-report chapter says its 3nm SoIC stacking entered volume production in 2025. The same report describes CoWoS as integrating multiple SoC chips and HBM stacks for HPC products. These statements support a description of TSMC’s published maturity claims, not an assertion that it has superior yield or performance. TSMC 2025 annual report, 3DFabric chapter
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What the major technology approaches disclose
TSMC: CoWoS, SoIC and a combined platform
TSMC’s published portfolio spans side-by-side 2.5D integration and vertical stacking. CoWoS is positioned for HPC and AI packages, with CoWoS-R using an RDL interposer for SoC and/or HBM. TSMC also describes SoIC stacking within its 3DFabric family and reports 3nm SoIC volume production beginning in 2025.
For a buyer, the key question is not whether these names exist but whether the exact package dimensions, HBM count, die-to-die links, thermal solution and design-kit release are available for the product’s tape-out and ramp dates. The 5.5-times-reticle CoWoS statement is a future-volume target as presented by TSMC, so it belongs in a schedule-risk register until qualification and capacity commitments are documented.
Intel: EMIB bridges and Foveros stacking
Intel’s U.S. advanced-packaging material describes EMIB silicon bridges, EMIB-T and Foveros stacking. Intel says EMIB-T adds channels through the bridge for power delivery and routing requirements associated with newer HBM technologies. That is Intel’s design rationale; a chipmaker should validate the claimed channel, power and signal requirements against its own package simulation and qualification data. Intel’s U.S. advanced packaging article
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Bridge-based and stacked options can be attractive when a design needs modular dies or a vertical connection, but they impose their own constraints on thermal paths, test access and known-good-die management. The decision should be made from package-level signoff data rather than from the architecture label alone.
Samsung: Chip-on-Wafer and heterogeneous integration
Samsung’s heterogeneous-integration page describes Chip-on-Wafer technology for 2.5D packages with higher HBM module counts and says it is developing fine-pitch bumpless hybrid copper bonding for HPC. Those statements identify Samsung’s stated offering and development work; they do not provide independent comparative measurements of bandwidth, yield or cost. Samsung Advanced Heterogeneous Integration
On July 25, 2026, Samsung announced a collaboration with Broadcom covering HBM supply and advanced packaging technologies, including 2.3D and 2.5D integration for next-generation AI accelerators. The announcement is a strategy and partnership signal. It is not proof that every described package is generally orderable or qualified for every customer. Samsung and Broadcom strategic collaboration announcement
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How procurement evaluates capacity, cost and schedule
Qualified capacity, not headline capacity
Package capacity must be expressed in qualified units for the specific design, not in a supplier’s theoretical maximum. Request a month-by-month ramp plan covering wafer starts, interposer or bridge processing, HBM receipt, assembly, burn-in, final test and shipping. Identify the bottleneck step and the recovery time if it slips.
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Total cost of ownership
A comparable quote should separate logic wafers, interposers or bridges, substrates, HBM, assembly, test, mask or reticle charges, engineering lots, requalification and logistics. The reviewed public sources do not provide neutral prices, yields or lead times. Treat any such value as design-specific and obtain it under nondisclosure agreements before making a financial commitment.
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Yield and risk sharing
Ask how yield is measured at wafer, known-good-die, package and final-test stages. Clarify who pays for scrap, rework, package redesign and HBM substitutions. A low wafer price can be outweighed by poor package yield if several expensive HBM stacks are lost with one defective package.
Schedule protection
Build the plan around qualification evidence, not a press-release date. Require entrance and exit criteria for design enablement, first silicon, package assembly, reliability testing, HBM interoperability and customer-system validation. Include a second-source or package-compatible fallback only if the architecture and design rules make migration realistic.
A practical scorecard for choosing among foundries
Use a weighted scorecard after each candidate supplies design-specific evidence. The weights should reflect the product’s failure costs; an early-generation accelerator may weight time to qualification more heavily than unit cost, while a high-volume product may do the opposite.
| Decision axis | Evidence to request | Why it matters |
|---|---|---|
| Package architecture and interconnect | Package design kit, routing limits, interposer or bridge dimensions, HBM interface models and thermal analysis. | Determines whether the intended die and memory arrangement can be built and cooled. |
| HBM configuration and supply | Qualified stack types, suppliers, part numbers, allocation terms and substitution procedure. | Prevents a package design from depending on unavailable or unqualified memory. |
| Logic process and design fit | Node rules, libraries, IP, EDA compatibility, die-to-die signoff flows and tape-out schedule. | Reveals whether the design can close electrically and physically. |
| Production maturity | Volume-production evidence, qualification reports, reliability data and ramp milestones. | Separates shipping capability from certification or roadmap language. |
| Ecosystem and operating model | Packaging engineers, EDA/IP partners, design-support coverage and responsibility matrix. | Shows how many interfaces the chipmaker must manage and where accountability sits. |
| Capacity, cost, yield and lead time | Binding quotes, reserved capacity, yield definitions, delivery dates and escalation terms. | These determine economic viability, but public sources reviewed here do not state comparable values. |
Red flags that can invalidate a foundry choice
- A package is described as “HBM-ready” without naming the supported HBM configuration or qualification status.
- A future volume-production date is treated as if it were a completed ramp.
- Capacity is quoted for wafers but not for assembled, tested packages.
- Yield is reported at a convenient stage that excludes HBM, assembly or final test losses.
- The chipmaker has no owner for coordinating logic, memory, package, substrate and test suppliers.
- A design kit or IP block is promised after the tape-out date.
- A partnership announcement is interpreted as a guaranteed allocation or universal customer availability.
What a decision memo should contain
Before signing a long-term agreement, document the selected package architecture, die and HBM bill of materials, process and design-kit revisions, qualification gates, capacity reservation, price formula, yield definitions, liability for rework, change-notification rules and exit options. Attach the supplier’s evidence for every production milestone and mark each item as achieved, in qualification, developmental or planned.
The memo should also state which claims come from vendor descriptions and which are verified for the chipmaker’s own design. That distinction keeps a marketing roadmap from silently becoming a financial forecast.
The bottom line for AI chip sourcing
The defensible choice is the foundry combination that can deliver the required logic process, HBM configuration and package at the needed volume and date with documented qualification and an accountable ecosystem. TSMC, Intel and Samsung describe different 2.5D, bridge and 3D capabilities, but the public material does not establish a universal winner or comparable cost, yield, lead-time or customer-allocation figures. A chipmaker should therefore select by design-specific evidence and signed capacity commitments, while treating roadmaps and partnerships as inputs to diligence rather than guarantees.
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