AMD is fabless at the wafer level, but not independent of manufacturing. It designs CPUs, GPUs, FPGAs and adaptive chips, while outsourcing wafer fabrication, assembly, testing and much of packaging. TSMC supplies AMD’s 7-nanometer-and-smaller CPU and GPU wafers; GlobalFoundries remains important for selected larger-node products, while UMC and Samsung serve certain programmable-logic products. The result is a model that is highly capital-efficient and technologically powerful—but exposed to concentrated foundry, packaging and geopolitical risks.
What “fab-light” means for AMD
“Fabless” means AMD does not own or operate the wafer fabs that manufacture its mainstream silicon. “Fab-light” is broader and less precise: AMD has limited direct wafer manufacturing, but it still performs substantial manufacturing-related work, including product qualification, process selection, packaging architecture, demand forecasting, capacity planning, inventory management and supplier coordination.
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The practical chain is:
AMD design and intellectual property → foundries → advanced packaging, assembly and test partners → memory, substrates and system integration → customers.
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Which companies manufacture AMD products?
| Supply-chain layer | AMD’s current position | Strategic implication |
|---|---|---|
| Leading-edge CPU and GPU wafers | TSMC manufactures all AMD microprocessor and GPU wafers at 7 nm or smaller nodes. | Access to advanced technology, but significant concentration in one foundry. |
| Larger-node CPU and GPU wafers | GlobalFoundries is used primarily for products above 7 nm. | Useful mature-node diversification and capacity commitments. |
| Programmable-logic products | AMD also uses UMC and Samsung for certain products. | Supplier diversity exists, but suppliers are not interchangeable on short notice. |
| Assembly, test, marking and packaging | Outsourced to partners including Tongfu joint ventures, SPIL and KYEC. | Finished-chip supply depends on more than wafer output. |
AMD’s GlobalFoundries agreement provides minimum annual capacity allocation and pricing through 2026. If AMD’s requirements fall below the applicable purchase target, the arrangement can create excess inventory or higher unit costs. GlobalFoundries itself reported that wafer fabrication and finished-wafer sales represented about 89% of its 2025 revenue; that figure is company-wide, not AMD-specific: GlobalFoundries 2025 annual report.
Why AMD abandoned an integrated-fab model
Owning a leading-edge fab is not simply a matter of constructing a building. It requires multibillion-dollar capital spending, continuous process development, equipment integration, yield learning, high utilization and frequent transitions to new nodes. A company must keep the factory busy while competing with much larger customers for equipment, talent and process-learning resources.
For AMD, internal fabs would also compete for capital and engineering attention with CPU architecture, GPUs, chiplets, software, acquisitions and complete data-center platforms. A specialized foundry can spread fixed costs and process-learning expenses across many customers. AMD buys access to that scale while concentrating its own resources on differentiated design and software.
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AMD reported fiscal 2025 revenue of $34.6 billion, 50% GAAP gross margin, $3.7 billion of GAAP operating income and $4.3 billion of GAAP net income. In the quarter ended March 28, 2026, revenue was $10.253 billion, GAAP gross margin was 53%, and data-center revenue reached $5.8 billion, up 57% year over year. The figures come from AMD’s earnings releases and slides: fiscal 2025 results and Q1 2026 results.
Those results demonstrate scale and financial strength, not proof that fablessness automatically produces superior margins. Gross margin also reflects product mix, pricing, inventory charges, export controls, packaging costs, amortization and competition. AMD still pays foundry prices that reflect advanced-process scarcity. Capacity reservations, prepayments, minimum purchases and inventory buffers reduce the apparent “asset-light” advantage.
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Why TSMC is both an advantage and a vulnerability
TSMC reported more than 17 million 12-inch-equivalent wafers of annual capacity in 2025 and said its 2 nm process entered high-volume manufacturing in the fourth quarter of that year. It is also expanding advanced packaging and three-dimensional integration: TSMC capacity information and TSMC 2025 annual report.
That scale lets AMD adopt leading-edge processes without funding a comparable fab network. It also supports a heterogeneous strategy: advanced-node compute chiplets can be combined with mature-node I/O dies and other components. But TSMC-wide capacity is not AMD-dedicated capacity. TSMC serves many major customers, and AMD warns that suppliers may increase prices, require onerous prepayments, fail to meet quantities or prioritize competitors.
TSMC dependence is therefore a two-sided proposition:
- Advantage: access to scarce process technology, packaging expertise and a broad manufacturing ecosystem.
- Vulnerability: AMD cannot independently fix a capacity shortage, yield problem, major outage or Taiwan-related disruption.
Chiplets move the bottleneck rather than remove it
Chiplets allow performance-critical compute dies to use an advanced node while I/O, memory controllers and other functions use less expensive mature nodes. Smaller dies can improve yield, validated building blocks can be reused, and product variants can be created more efficiently.
However, a chiplet product is a manufacturing system. It depends on die-to-die interconnects, package-level power delivery, thermal engineering, assembly yield, substrates, testing and often high-bandwidth memory. AMD’s annual report identifies packaging technology and manufacturing yield as factors that can affect unit cost, gross margin, supply and customer allocation.
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For AI accelerators, a wafer is not a sellable product. The dies must be assembled into a qualified package, connected to memory, tested and integrated into a system. Chiplets reduce the risk of one enormous monolithic die, but increase coordination requirements across packaging and test suppliers.
The hidden manufacturing bill
- Capacity commitments: Reserved wafers improve visibility but can create minimum-volume and excess-inventory exposure.
- Packaging and substrates: Advanced packages and high-bandwidth-memory integration can become bottlenecks after wafers are available.
- Yield and qualification: New dies, processes and packages require learning and customer validation; poor yields raise cost and limit supply.
- Inventory: Buffers protect customers during shortages but become costly if demand forecasts fail.
- Logistics and materials: Finished-chip availability depends on shipping, chemicals, equipment, substrates and memory suppliers.
GlobalFoundries and the value of mature nodes
Not every transistor benefits equally from the newest process. I/O, analog, connectivity, power-management and embedded functions can be economical on mature or specialty nodes. AMD’s GlobalFoundries relationship provides capacity and pricing visibility for selected products while its newest compute dies rely on TSMC.
This is diversification, but not instant substitutability. Moving a design between foundries may require porting, new process-design kits, mask sets, package and test flows, requalification and customer validation. A leading-edge CPU or GPU cannot normally be transferred to another supplier on short notice.
Advanced packaging is becoming a strategic manufacturing layer
AMD announced in May 2026 more than $10 billion in investments across the Taiwan ecosystem to expand strategic partnerships and advanced-packaging manufacturing for next-generation AI infrastructure, including work with ASE, SPIL and other partners on wafer-based 2.5D bridge-interconnect technology: AMD’s Taiwan ecosystem announcement.
The announcement concerns ecosystem investments and partnerships, not AMD purchasing and operating $10 billion of wafer fabs. It nevertheless shows why “fabless” is an incomplete description. AMD may not own leading-edge fabs, but it can help shape packaging capacity, qualification and integration around them.
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Stress tests for the strategy
TSMC capacity shortage
Strong demand with insufficient wafer allocation could force product rationing, delayed shipments, lost revenue and prioritization of the highest-margin products.
New-node or package yield problem
Lower-than-expected yield increases the cost per usable chip, reduces supply and can delay a product ramp.
Advanced-packaging bottleneck
Wafers may be available while packaging, substrates, HBM integration or testing capacity is constrained. The finished accelerator cannot ship until all layers are ready.
Demand forecast error
If AMD commits to capacity or inventory for expected AI demand that does not appear, it can face excess stock, reserves, minimum-purchase costs and lower margins. The GlobalFoundries agreement illustrates this trade-off.
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Manufacturing execution can succeed while regulation creates financial damage. AMD reported approximately $440 million in fiscal 2025 net inventory and related charges associated with U.S. export controls on MI308 data-center GPUs: AMD 2025 Form 10-K.
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Taiwan disruption
AMD identifies possible disruption involving Taiwan or China as a risk to foundries, manufacturing facilities and subcontractors. This is a disclosed scenario risk, not a forecast. Geographic expansion by TSMC can reduce some exposure but does not make the global equipment, materials, packaging and logistics network independent of Taiwan.
Myth versus reality
| Myth | Reality |
|---|---|
| Fabless means manufacturing risk is low. | AMD avoids fab ownership but remains exposed to foundries, packaging, materials, logistics and yields. |
| AMD simply buys chips from TSMC. | It coordinates multi-die design, process selection, packaging, testing, qualification and supply planning. |
| Chiplets eliminate manufacturing constraints. | They reduce monolithic-die risk while increasing dependence on advanced packaging and interconnect capacity. |
| TSMC dependence is purely negative. | It concentrates supply risk while providing access to a difficult-to-replicate technology ecosystem. |
| Owning fabs would automatically improve margins. | Ownership would add depreciation, utilization, process-transition and yield risks. |
| AMD has no manufacturing investment. | It invests in manufacturing-related capabilities and ecosystem partnerships, particularly packaging. |
Could AMD own leading-edge fabs again?
A return to full integration would offer more direct control, but it would require enormous capital, long development cycles, high utilization and simultaneous management of design and manufacturing road maps. It could distract from AI accelerators, CPUs, software and systems while exposing AMD to construction, yield and technology-transition risk.
The strategic question is therefore not whether AMD owns fabs, but whether it can secure economically viable, technologically competitive and geographically resilient capacity. The most plausible middle path is continued fabless wafer production combined with:
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- multi-year wafer commitments and capacity reservations;
- strategic investment in advanced packaging;
- joint development with foundries and outsourced assembly and test providers;
- multiple-node product designs;
- regional manufacturing options where technically practical; and
- larger inventory and supply buffers for strategic products.
This is an analytical conclusion, not a confirmed AMD plan.
How investors should judge AMD’s model
- Capital efficiency: Can AMD produce more architecture, software and platform innovation per dollar by outsourcing fabs?
- Technology access: Can it obtain advanced processes and packaging at a pace comparable with integrated competitors?
- Supply assurance: Can it secure wafers, packaging, memory and substrates during demand spikes?
- Geopolitical resilience: Does diversification reduce exposure without creating uneconomic duplication?
- Strategic flexibility: Can designs move across nodes or suppliers without costly redesign and requalification?
These tests are more informative than treating gross margin or the “fabless” label as a verdict.
The Bottom Line
Verdict: AMD’s fab-light strategy is a genuine competitive advantage in capital efficiency and access to advanced manufacturing—not an escape from manufacturing risk. AMD has concentrated that risk in TSMC and a smaller network of packaging, memory, substrate and logistics partners. The model remains compelling while AMD can secure predictable capacity, manage chiplet and packaging complexity, and build enough geographic and supplier resilience to withstand disruptions.
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