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Ainekko announced its merger with fabless semiconductor company Veevx on January 29, 2026, saying the combined company would keep the Ainekko name. The deal brought Veevx’s embedded-AI experience and MRAM-based iRAM memory into Ainekko’s open-silicon effort—but it did not establish that every part of the memory technology would be open source.
What did Ainekko gain by merging with Veevx?
Ainekko described the January 2026 merger as combining its open-silicon platform with Veevx’s iRAM memory technology, embedded-AI experience, and team. Ainekko had previously acquired intellectual property from Esperanto Technologies, including a many-core RISC-V architecture and toolchain. The merger announcement presented Veevx’s memory expertise as an addition to that foundation, rather than as a consumer product launch. Ainekko’s announcement and company description
Ainekko CEO Tanya Dadasheva framed the ambition this way: “We’re doing for AI hardware what Linux did for operating systems and Kubernetes did for cloud infrastructure.” That is the company’s analogy for its vision, not evidence that the platform has reached the maturity or adoption of those software ecosystems.
What is iRAM MRAM?
iRAM is Ainekko’s name for its MRAM-based memory technology. In its merger announcement, Ainekko described iRAM as high-density, non-volatile memory with SRAM-like performance, aimed at edge AI and embedded inference. Those are company characterizations; the announcement does not provide independent measurements establishing speed, power use, density, or commercial availability. Ainekko’s merger announcement
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MRAM’s non-volatility means it retains data without continuous power, unlike volatile SRAM. But the sources available for this announcement do not provide a like-for-like comparison of iRAM with SRAM or DRAM across performance, power, cost, or implementation maturity. Those trade-offs cannot be quantified from the announced information alone.
What was the first chip design supposed to show?
EE Times reported on January 30, 2026 that Ainekko planned its first tape-out for the beginning of Q2 2026 using a TSMC 16-nm shuttle wafer. The reported design paired eight Esperanto Minion small RISC-V cores with Veevx MRAM replacing some SRAM. EE Times described it as based on an earlier Veevx AI accelerator design, with Esperanto RISC-V cores replacing Arm cores. This was a plan reported in January; the sources reviewed do not confirm that the tape-out was completed. EE Times report on the merger and planned design
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In that report, Ainekko CTO Roman Shaposhnik said early indications suggested the MRAM implementation could reduce die area by about 25% compared with SRAM. This was a preliminary company estimate reported by EE Times, not an independently verified result from a completed product or published benchmark.
Is Ainekko’s MRAM technology open source?
Not necessarily in every layer. In a January 2026 EE Times interview, Ainekko said it intended to open-source RTL—the register-transfer-level design description—but had not decided how to handle Veevx’s analog-level MRAM technology. At that time, whether Veevx IP would become a commercial product was also undecided. Shaposhnik said, “We’re definitely open-sourcing everything at the RTL level.” The statement addressed RTL, not the analog implementation. EE Times interview on the open-source plans
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- Supplier Device Package 8-DFN-EP, Small Flag (5x6)
- Base Product Number MR25H10
- Package / Case 8-VDFN Exposed Pad
- Operating Temperature -40°C ~ 85°C (TA)
- Clock Frequency 40 MHz
In June 2026, Ainekko announced that its CORE-ET Silicon Platform had been accepted as an OpenHW Foundation project. The announcement says the platform includes many-core 64-bit RISC-V compute, vector/SIMD extensions, a network-on-chip architecture with MRAM-based memory, flexible system interfaces, an architecture emulator, and tools for AI inference frameworks. Ainekko says the architecture, RTL, and tooling are openly available. OpenHW Foundation news
That project update establishes an open status for the described CORE-ET architecture, RTL, and tools. It does not establish that iRAM’s analog-level implementation has been published, licensed for public use, or made available to developers. Ainekko’s site describes its substrate as open and lists the platform in AI Foundry and the OpenHW Group of the Eclipse Foundation; its GitHub repository presents a composable inference-to-hardware stack under an Apache-2.0 license. Neither fact, on its own, determines the licensing or accessibility of every component in the merger, especially analog MRAM IP. Ainekko platform description Ainekko’s GitHub repositories
Rank #4
- Package / Case 8-VDFN Exposed Pad
- Supplier Device Package 8-DFN (5x6)
- Base Product Number MR25H256
- Operating Temperature -40°C ~ 85°C (TA)
- Write Cycle Time - Word, Page -
What does the merger mean for RISC-V edge AI?
Ainekko’s stated direction is to combine RISC-V compute, MRAM-based iRAM memory, and an open software stack into composable silicon for edge-AI inference. In the January 2026 interview, Dadasheva said, “The chips themselves are not the goal for us,” describing a focus on composable building blocks and libraries and saying the company did not intend to sell chips in volume. That was the CEO’s stated business direction at the time, not a guarantee of current strategy or a report of commercial availability. EE Times interview with Ainekko’s CEO
For developers, the practical significance depends on what is actually released: architecture and RTL can support inspection and design work, while access to the analog memory implementation may involve separate licensing or availability. The public announcements reviewed establish the project’s broad open-silicon direction, but not the status of that specific iRAM IP.
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