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Draper said in an August 14, 2024 EE Times interview that it aimed to provide the U.S. Department of Defense with advanced chips by 2027. The proposed devices would use Intel Foundry’s 18A process and combine dies from multiple U.S. suppliers in secure, domestically performed advanced packaging. As of August 18, 2026, that date remains a target rather than a publicly verified delivery milestone.
The short version
- Draper is not proposing to build a conventional, high-volume wafer fab for this effort.
- Intel Foundry would provide access to its 18A process ecosystem, while Draper would contribute design and security expertise, integration, packaging, assembly, testing and trusted services.
- The proposed architecture uses chiplets: separate dies combined in one package to provide different functions.
- The plan addresses aging defense-node technology, low military chip volumes and supply-chain assurance.
- A design-kit relationship, tape-out or prototype would not by itself prove that a qualified chip had entered a weapon system.
What Draper said it wanted to deliver
The 2024 report described a secure design-to-package route for selected defense applications, including missile and hypersonic systems. Draper was developing designs with universities and commercial partners and was targeting tape-out within roughly 18 months of the interview. The intended result was a heterogeneous package containing an Intel 18A-based die alongside chiplets supplied by other U.S. companies.
That wording matters. Draper’s role was principally to connect design, security IP, Intel’s foundry ecosystem and domestic packaging—not to manufacture every die itself. The proposed chain was an ecosystem involving Intel Foundry, Draper, chiplet suppliers, universities and government programs.
What Intel 18A means here
“18A” is Intel Foundry’s name for a leading-edge process generation. It is not a claim that the chip uses an 18-nanometer transistor dimension. For Draper, the significance was access to a modern commercial process-design environment for defense designs, rather than relying exclusively on older, defense-specific manufacturing lines.
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Draper said it was working with Intel Foundry Services through the U.S. Military, Aerospace and Government (USMAG) Alliance and seeking access to Intel’s 18A process-design kit for universities and startups. Access to a process-design kit enables development; it does not guarantee wafer allocation, production availability or military qualification.
How the chiplet model would work
Separate dies for separate functions
A chiplet is a smaller die designed to operate with other dies inside one package. Compute, memory, analog, radio-frequency, sensing and security functions can therefore use different process technologies. Only the functions that benefit from the newest node need to use it.
Draper’s expected workflow
- Draper or a partner develops a system design and security architecture.
- The relevant leading-edge die is adapted to Intel’s 18A process-design ecosystem.
- Other U.S. suppliers provide compatible chiplets where a different process is preferable.
- Draper co-designs the package and die-to-die connections, then assembles the components.
- The package is tested and subjected to security, reliability, environmental and mission-specific qualification before any defense transition.
Draper describes its 3D heterogeneous-integration work as including die/package co-design, die-to-die connectivity, system validation and rapid iteration. Packaging is therefore a system-engineering task, not merely a final finishing operation.
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Inside Draper’s St. Petersburg facility
Draper opened its Advanced Packaging Facility in St. Petersburg, Florida, in July 2024. The company identifies the site as DMEA-certified and describes it as a secure, onshore facility for advanced packaging, assembly, testing, prototyping and integration. It is intended to serve government, defense-industrial-base, academic and selected commercial users under ITAR/EAR compliance and Department of Defense trust protocols.
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The expansion was partly funded by a $10 million Defense Production Act Title III award made in 2021. Draper’s stated capabilities include 3D heterogeneous integration and an open-access or open-foundry-oriented model. A facility’s DMEA status applies to the facility and its approved activities; it does not automatically certify every chip assembled there for a particular aircraft, missile or spacecraft.
Why the Pentagon needs another microelectronics path
Defense systems use older nodes
Draper told EE Times that many weapons remain standardized on older process nodes while commercial semiconductor development has advanced. Returning defense programs to the commercial progression curve is difficult after years of separate technology and procurement decisions.
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Military volumes are too small to drive a leading-edge ecosystem
Most defense programs do not buy enough chips to support a dedicated leading-edge production ecosystem. The Pentagon has acknowledged that a traditional trusted-foundry model did not create enough economic incentive for suppliers to keep pace with commercial technology. Partnerships with commercial foundries and shared packaging infrastructure can spread those costs across more users.
Trust involves the whole chain
For a defense chip, assurance questions include who designed it, which company supplied each die, where wafers were processed, where the package was assembled and tested, and whether counterfeit, altered or compromised components could be detected. The Department of Defense has been moving toward quantifiable assurance and a zero-trust approach rather than relying only on a conventional trusted-foundry label.
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| Participant or program | Role described in available sources |
|---|---|
| Intel Foundry | 18A process technology, process-design kits, technical access and foundry ecosystem support. |
| Draper | Design and security expertise, precision instrumentation, packaging, integration, testing and trusted services. |
| Other U.S. chip suppliers | Potential sources of chiplets; the 2024 report did not identify every participant. |
| Universities | Draper was reported to be working with MIT, the University of Connecticut and another undisclosed Pacific Northwest university. |
| Commercial semiconductor companies | Draper said it worked with GlobalFoundries, Honeywell, Texas Instruments and other providers. |
| Intel Foundry Chiplet Alliance | Draper later identified itself as a founding member of an alliance focused on interoperable and secure chiplets, advanced packaging, assembly design kits, EDA and reusable IP. |
How DARPA fits in
DARPA’s Electronics Resurgence Initiative and its 3D heterogeneous-integration and Next-Generation Microelectronics Manufacturing programs pursue the same broad national objective: accessible U.S. prototyping and advanced integration for defense, academic and industry users. Draper’s facility is related to that ecosystem, but the available material does not establish it as the DARPA NGMM center.
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DARPA research and ecosystem-building awards also do not prove that a Draper-designed chip entered DoD production. They support capabilities that could make such a transition possible.
Timeline and evidence status
| Date | Milestone | Status |
|---|---|---|
| 2021 | Draper’s packaging expansion received partial support from a $10 million DPA Title III award. | Confirmed by Draper. |
| July 2023 | Draper joined Intel Foundry Services’ USMAG Alliance. | Confirmed by Draper. |
| 2023 | DARPA advanced programs for domestic 3D heterogeneous integration and microelectronics manufacturing. | Confirmed program activity; not proof of a Draper production chip. |
| July 2024 | Draper opened its St. Petersburg Advanced Packaging Facility. | Confirmed by Draper. |
| August 14, 2024 | EE Times reported Draper’s aim to provide DoD advanced chips by 2027 and its roughly 18-month tape-out target. | Reported objective, not a delivery contract. |
| August 18, 2026 | No source identified here independently confirms tape-out, packaged-part delivery, qualification or DoD adoption of an 18A Draper chip. | Unverified. |
What would make the 2027 goal credible?
A meaningful follow-up would identify a named chip or program and document a completed or scheduled tape-out, confirmed Intel 18A manufacturing, the chiplet suppliers and package architecture, and test results. It would also need evidence of electrical, thermal, radiation, security and reliability qualification; a DoD customer, contract or prototype order; delivery of packaged parts; and a sustainable path to repeat procurement.
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Leading edge versus qualification
An advanced node can improve performance and efficiency, but military systems require configuration control, environmental testing, long-term reliability evidence and, where applicable, radiation tolerance. A laboratory prototype is not automatically deployable.
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Chiplets increase integration work
Multiple dies add thermal-management, die-to-die signaling, interoperability, testing and interface-security challenges. Responsibility for defects or changes can also be divided among several suppliers.
Open access must coexist with security
An open facility can attract universities and startups and improve equipment utilization. It must still protect classified work, controlled technology, design confidentiality, trusted personnel processes and component provenance.
Onshore does not mean every input is domestic
Domestic design, packaging and assembly do not establish that every wafer, substrate, material, EDA tool, intellectual-property block or manufacturing input is sourced in the United States. Claims about a wholly U.S.-based supply chain need to be defined and attributed.
Prototype success does not ensure program transition
A defense customer may choose a mature, already-qualified node because it costs less, has established suppliers or better fits a platform’s life-cycle needs. Packaging capacity, Intel production access and the economics of small orders could also limit adoption.
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Draper’s proposal was an attempt to connect Intel’s leading-edge commercial process technology with secure U.S. chiplet integration and advanced packaging. It was not evidence that Draper was building a new 18A wafer fab or that the Pentagon had already received such a chip. As of August 18, 2026, the 2027 objective should be treated as a development target until public evidence shows tape-out, packaged samples, qualification, a DoD transition customer or delivery.
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