Ventana Micro Systems’ $55 million funding announcement in August 2022 was a bet on bringing high-performance RISC-V processors to data-center and other infrastructure markets through chiplets. The company aimed to tape out its first UCIe-based chiplet products in the second half of 2023. That was a forecast, not evidence of a completed tape-out or deployment. Ventana later advanced its Veyron processor family, and Qualcomm announced its acquisition of the company in December 2025. The funding story is therefore best understood as an early commercialization milestone, with important questions about product availability and customer deployment still distinct from the roadmap.
What Ventana announced in 2022
Ventana emerged from stealth with a $55 million funding announcement discussed by CEO Balaji Baktha in an interview published August 15, 2022, during the 59th Design Automation Conference in San Francisco. The stated purpose was to productize high-performance RISC-V compute chiplets for data-center, edge, automotive and 5G workloads. EE Times reported the funding and the company’s plans; RISC-V International also reposted the coverage.
Baktha said Ventana expected its first UCIe-based chiplet products to tape out in the second half of 2023. Tape-out means a design is submitted for fabrication; it does not establish that working silicon was produced, qualified, supported in software or deployed by a customer. The 2022 date should be read as a company target, not as a confirmed delivery milestone.
The round was intended to fund the difficult transition from CPU architecture and design to a product customers could incorporate into a system. The reported coverage does not identify all investors or provide a detailed financing filing, so it does not support a more precise breakdown of the round.
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What Ventana’s business model was
Ventana was not chiefly pitching a retail server processor. Its model centered on high-performance RISC-V CPU IP and compute chiplets that semiconductor companies, system vendors and other customers could use in custom platforms. The intended system could combine CPU chiplets with I/O, memory interfaces, accelerators and other specialized dies. Ventana describes its designs as usable in custom platforms and delivered in chiplet form, with RISC-V and die-to-die options including UCIe or BoW. The company’s overview describes that platform approach.
RISC-V is an instruction-set architecture, not a finished processor. Its openness gives designers room to build their own implementations and use applicable standard or custom extensions; it does not make a commercial CPU design free, guarantee software compatibility, or ensure better performance than Arm or x86. Ventana’s proposition was to pair that architectural flexibility with a high-performance implementation and a delivery model suited to custom silicon.
Why use chiplets for data-center processors?
A conventional monolithic processor places most or all major functions on one large die. A chiplet design divides functions among multiple dies connected inside a package. That can let designers use different process technologies for different functions, reuse CPU dies across products, scale core counts, or add workload-specific accelerators without redesigning one enormous die each time.
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For a cloud or infrastructure customer, the appeal is potential platform customization: a CPU compute die could be paired with I/O, memory and acceleration suited to a particular workload. But chiplets are not an automatic cost or power saving. Advanced packaging adds design and manufacturing demands; die-to-die signaling consumes power and package area; and multi-die systems require coordinated testing, thermal management, power delivery, firmware and software validation. Whether the economics work depends on the package, production scale, yield, workload and support model.
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UCIe, or Universal Chiplet Interconnect Express, is an open specification for communication between chiplets within a package. Its purpose is to make the die-to-die interface more standardized, rather than requiring every chiplet pairing to rely on a wholly bespoke connection. Ventana said it was working strategically with Intel around UCIe and high-performance RISC-V solutions. Intel’s 2022 fact sheet listed Ventana among its RISC-V ecosystem partners, while Intel Foundry now presents UCIe as part of an open chiplet ecosystem. Intel’s 2022 fact sheet and its chiplet platform page describe that context.
That relationship is evidence of ecosystem and technology cooperation, not an acquisition, a confirmed Intel manufacturing contract, or a disclosed deployment by Intel customers. Nor does an open interface by itself make any two chiplets work together. A product still needs compatible physical-layer IP, package and substrate design, protocol and coherency choices, interoperability testing, known-good-die methods, thermal and power planning, and a manufacturing and packaging path. The full platform also needs boot firmware, operating-system support, drivers, compilers and accelerator software.
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- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
What customer interest Ventana disclosed
In the 2022 interview, Baktha said new investors helped open markets in Taiwan, South Korea and Japan. He described interest from hyperscalers, particularly in China and also in the United States, and from European high-performance-computing buyers. He said a large Chinese cloud provider was expected to adopt RISC-V and that Ventana was working with a Chinese hyperscaler on infrastructure solutions. He also cited an expected major U.S. data-center infrastructure deployment in the second half of 2023, an automotive manufacturer engaged on an ADAS processor, and interest in 5G Open RAN and Chromebook-related work. These were company-reported business-development claims, not independently verified customer announcements. The interview is the source for those statements.
The public account did not name most customers or disclose contract values, purchase volumes or proof of deployment. Interest, evaluation and engagement can indicate a market opportunity, but they are not purchase orders or evidence that a system entered production. The expected U.S. deployment date in particular should not be recast as a confirmed event.
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How the Veyron roadmap evolved
Ventana’s later product story centered on Veyron, which the company positions as a data-center-class RISC-V processor family. Its official technology page describes Veyron V2 as licensable IP and says silicon platforms were launching in early 2026. Ventana’s news materials describe Veyron V2 in chiplet and IP forms. These are company product and roadmap statements; they do not by themselves establish production volume or broad customer deployment. Ventana’s Veyron technology page provides its current positioning.
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- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
| Period | What was stated | What that establishes |
|---|---|---|
| August 2022 | Ventana announced $55 million in funding and described a plan to productize RISC-V chiplets; first UCIe-based product tape-out was expected in the second half of 2023. | A financing announcement and forward-looking target, not proof of tape-out or deployment. EE Times |
| Later Veyron roadmap | Ventana presented Veyron V1 as its first data-center-class RISC-V processor family and Veyron V2 as a next-generation offering in IP or platform form. | Company product positioning; it does not independently verify customer volume or production performance. Ventana |
| December 10, 2025 | Qualcomm announced it had acquired Ventana, citing deeper RISC-V CPU expertise, including for edge and data-center applications. | A strategic corporate transaction, not proof of a particular deployment or revenue level. Qualcomm |
| Early 2026 roadmap language | Ventana’s technology page said Veyron V2 silicon platforms were launching in early 2026. | A company availability statement. The materials cited here do not independently establish broad commercial deployment, shipment volume or named hyperscaler adoption. Ventana |
The original 2023 target and later Veyron V2 timing are separate roadmap statements. Without independent confirmation, neither should be treated as evidence that the specific 2022 tape-out target was met.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What Qualcomm’s acquisition changes
Qualcomm announced the acquisition of Ventana on December 10, 2025, saying the deal would deepen its RISC-V CPU expertise, including for edge and data-center applications. Qualcomm’s announcement makes Ventana’s later corporate context essential: it is no longer best described simply as an independent startup.
The acquisition indicates that Ventana’s technology and team had strategic value to a major chip company. It does not establish that the purchase was driven by a specific hyperscaler contract, disclose a commercial performance result, or prove large-scale deployment. Qualcomm ownership may bring resources and affect licensing, product availability, roadmap control and partner access; the announcement alone does not settle how those questions will play out for individual customers.
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- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
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What a data-center buyer would need to verify
A CPU’s instruction set and peak core performance are only part of a server decision. A buyer considering a Ventana-style RISC-V chiplet platform would need evidence on the workload, complete system, software stack and commercial commitment.
Workload and performance evidence
- Match the system to the intended job: general cloud compute, AI inference, storage, networking, security appliances or another specialized workload.
- Ask for measured results on production silicon, distinguishing them from simulation, emulation or pre-silicon estimates.
- Compare benchmarks only when compiler settings, power limits, memory configuration and process generation are comparable. Useful workload-specific evidence may include CPU, database, networking or AI benchmarks rather than a single headline number.
Software and platform completeness
- Check operating-system, hypervisor, compiler, container and package support, including who maintains updates and for how long.
- Verify virtualization, IOMMU, memory coherency, PCIe, RAS features, secure boot, firmware and management-controller support.
- For accelerators, establish that drivers, libraries and developer tools support the intended workload and that the software stack is production-ready.
Packaging, supply and economics
- Confirm the actual die-to-die interface, foundry and advanced-packaging route, test strategy, capacity and supply-chain geography.
- Model package-level power, thermal behavior, yield and system cooling rather than assuming chiplets reduce total cost or energy use.
- Get clarity on licensing terms, non-recurring engineering charges, minimum volumes, customization schedule, warranty and long-term support. Public materials cited here do not provide a standard price list.
Vendor and migration risk
Moving from an x86 or Arm software estate has costs beyond replacing a CPU: applications, operating images, performance tuning, operational tooling and support arrangements may all need work. Qualcomm’s ownership could strengthen the resource base behind the platform, while also changing customer access or roadmap priorities. Buyers should assess those commercial terms directly rather than infer them from the acquisition announcement.
What the $55 million funding ultimately signified
The 2022 raise was significant because it was meant to finance commercialization across several hard problems at once: a high-performance RISC-V CPU, chiplet integration, an open die-to-die interface and a customer-ready system platform. The subsequent Veyron roadmap and Qualcomm acquisition show continued strategic interest in the technology. They do not, on the evidence cited here, turn the original forecasts into verified deployment results. For data-center buyers, the decisive evidence remains a qualified platform, comparable measured performance, production support and a credible supply commitment.
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