On December 10, 2002, TSMC announced an expanded library program covering 0.15-micron, 0.13-micron and Nexsys 90nm processes. Its plan paired TSMC-developed and third-party design libraries with distribution and support from external partners: Virage Logic was the first partner named. The announcement’s focus was semiconductor design infrastructure—not a consumer product or a current offer.
What TSMC announced
TSMC’s announcement described a library service for several process generations, rather than a single 90nm product. The program included TSMC-developed and third-party libraries, while multiple library and electronic-design-automation (EDA) partners would distribute and support TSMC-branded standard-cell and I/O libraries. TSMC said it would identify additional partners in the following weeks. TSMC’s December 10, 2002 announcement is the primary record of the plan.
A contemporaneous EE Times report published December 9, 2002 said TSMC was considering whether to continue direct customer support for its internally developed libraries as it added distribution partners. That was reporting on a question under consideration, not a final policy statement from TSMC.
What was in the Nexsys 90nm libraries
TSMC identified standard cells and I/O cells as part of the Nexsys 90nm library set. It also highlighted Dual-Threshold Power Tuning, which the company said let designers put high-speed and low-leakage functionality on the same chip. These process-specific design assets gave chip designers building blocks suited to a particular manufacturing process; they were not general-purpose software or finished chips.
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TSMC’s rationale was that no single library could suit every design. Ed Chen, then director of design and e-service in TSMC’s marketing division, pointed to trade-offs among density, speed and power, noting that high-speed GPUs and handheld PDAs could call for different choices. The practical implication is that “better” depended on the chip’s goals and constraints, not simply on the process node.
How the distribution strategy developed
| Date | What was announced | What the timing establishes |
|---|---|---|
| December 10, 2002 | TSMC named Virage Logic as the first partner in its expanded library program for 0.15-micron, 0.13-micron and 90nm technologies. TSMC announcement. | Virage Logic was the first partner named in the original announcement, not necessarily the only partner in the program. |
| January 13, 2003 | Cadence and TSMC announced a design-flow collaboration. Cadence described itself as the first full-line distributor of TSMC-developed standard-cell and I/O libraries and memories, integrating them with Encounter and the TSMC Reference Flow. Cadence announcement. | This was a later distribution and integration announcement; it does not change which partner TSMC first named in December 2002. |
| February 1, 2005 | TSMC described a full suite of internally developed libraries supporting Nexsys 90nm production, and named Cadence, Synopsys, Artisan, Magma Design Automation and Virage Logic as distribution partners. TSMC announcement. | This is the partner list reported in 2005, not a complete list for the 2002 announcement. |
Working through partners could put libraries alongside EDA tools and established design flows, with partners handling distribution and support. Cadence’s 2003 announcement illustrates that integration approach: its Encounter flow was qualified for the TSMC Reference Flow. The announcements support that explanation, but do not establish the details of each partner’s support obligations or TSMC’s eventual direct-support policy.
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How to interpret TSMC’s performance and density figures
TSMC’s 2002 announcement claimed up to 50% performance improvement, with half the area and half the power compared with a 0.13-micron library. These were company-reported comparisons, not independent test results; the announcement’s wording does not establish that every design would achieve those results. In 2005, TSMC said its libraries reached 420,000 gates per square millimeter, about double the density of the 0.13-micron-generation libraries. That, too, was a vendor-reported historical figure, not a current benchmark. 2002 announcement; 2005 announcement.
What the later library suite covered
In 2005, TSMC described libraries for three process variants: general-purpose (G), high-performance (GT) and low-power (LP). It also named standard-cell, I/O, memory and specialty libraries as categories in its broader validated ecosystem. Those categories and variants help explain how the program served different design needs, but the 2005 description should not be treated as a specification of every library available in 2002.
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What the historical commercial terms do—and don’t—tell you
TSMC’s 2005 announcement said its libraries were free of charge and downloadable through distribution partners. EE Times reported in December 2002 that TSMC libraries would be free but subject to royalties based on the number of chips produced, while Virage Logic products would carry license and support fees. These are terms reported for that historical period, and the sources do not establish present-day pricing, access, licensing or partner status.
The evidence supports a concise account of a historical distribution strategy: TSMC broadened its library program across process generations, named Virage Logic first, and subsequently announced additional distribution and EDA-flow relationships. It does not establish that the libraries remain available today.
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