On May 17, 1999, TSMC announced that its CL018 0.18-micron CMOS process was available for production—and said it had already begun shipping 0.18-micron products. The launch paired a six-layer metal process using fluorinated silicon glass insulation with an ambitious capacity plan: 34,000 eight-inch wafers in 1999 and more than 600,000 in 2000. The expansion was to involve Hsinchu, WaferTech in Camas, Washington, and Fab 6 in Tainan.
What TSMC announced in May 1999
TSMC’s May 17 announcement concerned a production-ready foundry process, not just a research milestone. The company called it CL018 and said it had started shipping products made with the 0.18-micron CMOS technology. The process included six metal-interconnect layers and fluorinated silicon glass (FSG) as an insulating dielectric. EDN’s contemporaneous report described the launch and its technical specifications.
TSMC positioned the process as more than a straightforward shrink of a 0.25-micron design. Roger Fisher, then TSMC’s vice president of marketing, said: “Our observation is that many of the previously announced technologies have been shrinks of 0.25-micron processes, where primarily the gate length was reduced.” The distinction matters: the announcement described changes to interconnect pitch and insulation as well as smaller geometry, while the nominal 0.18-micron node alone does not specify every design dimension.
How the process was designed to improve density and interconnect performance
Six metal layers with progressively wider pitch
EDN reported a first-level metal pitch of 0.46 micron, 0.56 micron for each of the next four metal layers, and 0.90 micron for the sixth layer. The fine pitches were reported to support a density of 100,000 to 120,000 gates per square millimeter. That figure is a contemporaneous report, not a universal measure of the density achievable in every customer design.
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FSG insulation to reduce capacitance
The process used FSG, a low-k insulating material. EDN gave its dielectric rating as 3.3 to 3.4, compared with just above 4 for conventional silicon dioxide, and described the lower rating as a way to reduce capacitance. In practical terms, lower interconnect capacitance can help reduce signal delay, though the result in a finished chip depends on the design and implementation.
A planned second-generation variant
At launch, TSMC said it planned a second-generation 0.18-micron process for the third quarter of 1999. EDN reported a 0.13-micron drawn gate length for 1.5-volt core operation and higher device speeds. That drawn gate-length figure is not interchangeable with the process’s 0.18-micron node label.
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- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
How steep was the planned production ramp?
TSMC projected 34,000 eight-inch wafers for 1999 and more than 600,000 for 2000. These were company production plans stated in the May 1999 announcement, not a report of final output in those years. The scale of the planned increase—over 17 times the 1999 figure if the 2000 total reached 600,000—helps explain why the announcement also emphasized moving the process into multiple volume fabs.
Which fabs were part of the expansion?
- Hsinchu, Taiwan: TSMC planned to transfer the process to its volume plants there.
- WaferTech, Camas, Washington: TSMC planned to increase 1999 capital spending for the joint-venture fab as part of the ramp.
- Fab 6, Tainan, Taiwan: The company planned to equip the fab, which was scheduled to begin processing eight-inch wafers by April 2000.
The fab plans show that the ramp was not simply a matter of announcing a smaller process: TSMC tied volume availability to transferring the technology and equipping additional manufacturing capacity.
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How the copper option followed the baseline process
In a separate announcement on December 7, 1999, TSMC described a commercially available two-layer copper process designed to be compatible with its baseline 0.18-micron process. TSMC said the copper process initially entered production in its eight-inch Hsinchu fabs, with full production expected to include Fab 6 in Tainan. The company presented it as a turnkey offering that included the process, design services, testing, and support. TSMC’s announcement gives the company’s own account.
TSMC attributed the following performance figures to the copper process: 1.6-times lower metal resistance, up to 15% lower RC delay, 30-to-50-times higher electromigration reliability, and five-times lower via series resistance than tungsten plug vias. These are TSMC’s published claims; they should not be read as independently measured results for every design. TSMC president F.C. Tseng called it “the foundry industry’s first commercially available copper process” and said it would give semiconductor companies an opportunity to compete at the leading edge.
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What the announcement does—and does not—establish
The May launch establishes that TSMC announced production availability and product shipments for its CL018 process, and specified a substantial planned capacity ramp and participating fabs. It does not establish that the planned wafer totals were ultimately achieved. Nor should the later copper-process figures be confused with measured results for all baseline CL018 products: those numbers were company claims attached to the copper variant.
TSMC’s current technology page describes 0.18-micron logic as a mature, reliable, proven solution for a range of applications, but it does not document the 1999 ramp totals. TSMC’s logic technology page provides that present-day characterization.
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