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On October 12, 2004, TSMC and Freescale Semiconductor announced a three-year agreement to jointly develop 65-nanometer (65-nm) silicon-on-insulator (SOI) high-performance transistor front-end technology. Separately, TSMC received manufacturing rights to Freescale’s existing 90-nm SOI technology. The 65-nm work was a joint development plan—not a simple license of a finished Freescale process.
What the agreement covered
The announcement combined two distinct arrangements: shared development of a new 65-nm SOI transistor front end, and TSMC’s right to manufacture using Freescale’s 90-nm SOI technology. The companies said the collaboration was intended to accelerate the arrival of 65-nm SOI technology. It did not announce a completed process, a product launch, or broad customer availability. TSMC’s October 12, 2004 announcement set the public terms.
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Freescale had become a standalone semiconductor company after separating from Motorola. The corporate history matters because a later TSMC filing describes a related technology-development and licensing agreement with Motorola from December 2003. That earlier record does not, by itself, contradict the October 2004 announcement naming Freescale.
What SOI changes in a chip
In silicon-on-insulator technology, a thin insulating layer—typically buried oxide—separates the active silicon device layer from the underlying silicon substrate. That isolation can reduce parasitic capacitance between a transistor and the substrate. Lower capacitance can help a circuit switch faster or use less dynamic power, while electrical isolation can also benefit some radio-frequency and mixed-signal designs. These are potential, design-dependent advantages, not guarantees for every chip.
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SOI also brings trade-offs. Partially depleted SOI devices can exhibit floating-body effects that designers must account for. SRAM cells, circuit models, body contacts, and design rules may need process-specific treatment. The buried insulating layer can hinder heat flow, and SOI wafers generally cost more than ordinary bulk-silicon wafers. A bulk-CMOS design therefore does not automatically transfer to SOI unchanged.
The 2004 announcement described high-performance SOI CMOS; it did not identify the planned process as modern fully depleted SOI, or FD-SOI. Those terms should not be treated as interchangeable.
How the companies divided the work
Shared transistor front end, separate interconnects
The companies planned to work together on the transistor front end, where the device structure and SOI behavior are established. They would develop their 65-nm metallization back ends independently. Separate interconnect stacks could be tuned to each company’s products, design rules, performance and voltage targets, reliability needs, and manufacturing infrastructure. The announcement therefore did not promise one identical, end-to-end process at both companies.
Development in Austin, pilot work in France
The release located the joint 65-nm development project at Freescale’s Dan Noble Center in Austin, Texas. Freescale planned to apply the technology to chips at Crolles2, a 300-mm research-and-development and pilot-manufacturing facility in France associated with Freescale, Philips Semiconductors, and STMicroelectronics.
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Potential TSMC use in Taiwan
TSMC said it might apply the technology at its Taiwan facilities. Its announced targets included a high-speed version for networking and computing and a low-power version for handheld and portable devices. These were intended applications, not evidence that a particular product or customer later used the process.
Why 65 nm mattered in 2004
At the time, 65 nm was the next major CMOS logic node after 90 nm. Chipmakers were also moving toward 300-mm wafers, copper and low-k interconnects, and more complex transistor techniques. Manufacturers needed process variants for different priorities, including high performance and low power; companies without their own advanced fabs also depended on foundries.
TSMC’s 2004 annual report says the company had qualified a 90-nm CMOS logic process and demonstrated a baseline 65-nm CMOS platform, while continuing exploratory SOI work. The partnership was therefore one part of a broader 65-nm program, not TSMC’s entire roadmap. TSMC’s 2004 annual report provides that wider context.
What each company brought
Freescale’s SOI experience
Freescale’s announcement said the company had worked through three generations of SOI development since the mid-1980s and had shipped more than seven million SOI-enabled products since production began in 2001. Those figures are claims from the company’s 2004 release, not independently audited market totals. The release also cited a 90-nm CMOS SOI platform under development at the Dan Noble Center and Freescale’s experience in high-performance SOI products and manufacturing.
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TSMC’s foundry and process-development capability
TSMC brought foundry manufacturing experience, advanced CMOS process development, and an existing relationship with Freescale. The release said TSMC’s own SOI work dated to around the 0.13-micron generation. Combining that experience with Freescale’s SOI expertise offered a route to develop the front end jointly while preserving company-specific manufacturing choices.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.The competitive and alliance context
Contemporary trade coverage described IBM as a strong SOI foundry competitor and reported that some customers had chosen IBM for SOI-related work. That is useful context for why a stronger TSMC SOI offering could matter, but it is not proof that a particular lost contract caused the TSMC–Freescale agreement. EE Times’ coverage from that week and EDN’s report discuss the competitive backdrop.
Crolles2 also placed the plan within a wider European process-development alliance involving Freescale, Philips, and STMicroelectronics. TSMC’s later filing refers to a December 2003 agreement with Motorola covering joint 65-nm SOI development and related 90-nm licensing. Read alongside Freescale’s corporate separation, that chronology suggests continuity in the relationship; the public records do not establish every contractual detail of how the earlier agreement related to the October 2004 announcement. TSMC’s filing describes the earlier Motorola agreement.
What later records establish—and what they do not
A later SEC filing says the Crolles alliance developed 90-nm and 65-nm technologies and that early-stage 65-nm production began in early 2006. This supports the broader account of 65-nm development progressing toward production, but it does not show that the October 2004 agreement alone caused that outcome. Nor does it identify a specific commercial product using the joint front end or establish that TSMC’s Taiwan implementation used every Crolles process module. The later SEC filing documents the Crolles-related progress.
The October 2004 announcement did not disclose licensing fees or royalties, capital spending, wafer volumes, named launch customers, yield targets, exact transistor performance, product schedules, or whether TSMC would offer the resulting platform broadly to third parties. Those outcomes should not be inferred from the agreement’s announcement.
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