Rapidus’s 2-nm pilot line is no longer a future opening. The Japanese semiconductor company began operating the line at its IIM-1 facility in Chitose, Hokkaido, in April 2025. It later reported electrically operating 2-nm gate-all-around transistor prototypes in July 2025.
The more consequential question now is whether Rapidus can turn those pilot-stage achievements—and extensive Japanese government backing—into reliable, affordable, high-volume manufacturing targeted for 2027.
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What Rapidus actually opened
Rapidus opened a pilot line inside IIM-1, its “Innovative Integration for Manufacturing” research and manufacturing hub in Chitose, Hokkaido. The facility is intended to support development and eventual mass production of advanced logic semiconductors using a 2-nm-class process. Rapidus broke ground on IIM-1 in September 2023 and installed an ASML extreme ultraviolet, or EUV, lithography system in December 2024. Rapidus describes the facility and its timeline here.
A pilot line is not the same as a fully ramped production fab. It is used to qualify equipment, refine manufacturing steps, measure transistor characteristics and produce prototype wafers for potential customers. A commercial fab must go further: it must produce large volumes consistently, with acceptable yields, cycle times, reliability and costs.
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Rapidus says mass production is targeted for 2027. That is a company goal, not a guarantee that commercially competitive output will be available immediately at the start of that year.
What “2-nm” means
“2-nm” is a semiconductor process-node label. It should not be read as saying that every transistor feature or circuit dimension is exactly two nanometers wide. Node names are not directly comparable physical measurements across manufacturers.
Rapidus’s process uses gate-all-around, or GAA, transistor architecture. Earlier FinFET designs surround the channel on three sides. GAA designs surround the channel more completely, improving electrostatic control and potentially reducing leakage as transistors become smaller. Rapidus has developed its process partly through technology collaboration with IBM. The company’s CEO interview explains its GAA and manufacturing strategy.
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The practical value of a 2-nm-class process depends on more than the label. Customers will care about power consumption, performance, transistor density, defect rates, reliability, design support and the cost of usable chips.
What Rapidus has demonstrated so far
The evidence shows meaningful technical progress, but it does not yet establish high-volume manufacturing:
- December 2024: Rapidus installed an ASML EUV system at IIM-1.
- April 2025: The pilot line began operation.
- July 18, 2025: Rapidus said its first 2-nm GAA transistors had achieved electrical operation.
- Early customer enablement: The company planned a process design kit, or PDK, for prospective customers, initially targeted for the first quarter of 2026.
Rapidus has said its pilot work involves 300-mm wafers and prototype transistor structures. Reporting by Tom’s Hardware noted that the company was measuring characteristics such as threshold voltage, drive current, leakage current and subthreshold slope, but that detailed results were not disclosed.
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That distinction matters. An electrically operating prototype demonstrates that a process can produce functioning devices under test conditions. It does not by itself prove a repeatable production yield, competitive economics or customer-ready chips.
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Why Rapidus emphasizes single-wafer processing
Rapidus has promoted a manufacturing approach based on processing wafers individually through front-end process steps rather than relying on conventional batch processing. The company argues that this can improve process control, accelerate learning and shorten the time needed to adjust manufacturing conditions.
It also plans to use artificial intelligence and detailed wafer-level data to help optimize processes. Rapidus says about 150 engineers were trained or worked with IBM and imec during development, and that the pilot line contains more than 200 new machines.
Single-wafer processing may help engineers identify problems quickly, but it is not automatically a throughput or cost advantage. A production foundry must also keep equipment highly utilized and move enough wafers through the line at a cost customers will accept. Whether Rapidus’s approach improves commercial performance remains an open question.
The IBM partnership reduces risk—but does not remove it
Rapidus and IBM entered a strategic partnership in December 2022. Rapidus sent engineers to IBM’s Albany Nanotech Complex in New York to work on technology intended for 2-nm-generation volume production. Rapidus’s company timeline describes the partnership and development milestones.
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Why Japan is backing the project
Rapidus is part of Japan’s effort to rebuild domestic capability in leading-edge logic semiconductors. Japan remains important in semiconductor materials, equipment and memory, but it lost much of its former position in advanced logic foundry manufacturing.
Government policy views domestic advanced-chip capability as an economic and supply-chain priority. A leading-edge foundry could support Japanese industries such as automotive, robotics, telecommunications and industrial electronics while reducing reliance on overseas manufacturing for strategically important systems. Japan’s broader policy rationale is outlined by its Ministry of Economy, Trade and Industry.
The financial support also spreads the risk of rebuilding an extremely expensive industry. But state backing should not be confused with commercial validation. Public funding can finance buildings, equipment and development; it cannot guarantee customer demand, manufacturing yields or profitability.
Rapidus’s latest funding
On February 27, 2026, Rapidus announced a funding round totaling ¥267.6 billion:
- ¥100 billion from Japan’s Information-Technology Promotion Agency.
- ¥167.6 billion from 32 private-sector companies.
- Investors included Canon, Fujitsu, NTT, SoftBank, Sony, Toyota, Kioxia and IBM Japan, among others.
Rapidus’s funding announcement provides the full public-private breakdown.
This is substantial financing, but a leading-edge foundry requires continuing investment in equipment, process development, staffing, materials, packaging and capacity. The amount raised does not establish that Rapidus has secured all the capital it will ultimately need.
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What “mass production in 2027” must prove
Rapidus’s 2027 target should be evaluated as a ramp, not a single opening-day event. The first production wafers would not necessarily represent sustained high-volume manufacturing.
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- Yield: What percentage of dies are usable and saleable?
- Performance and power: Do finished chips meet customer specifications?
- Reliability: Do devices pass qualification and long-duration testing?
- PDK maturity: Can outside designers create working layouts without extraordinary engineering support?
- Customer tape-outs: Have named customers submitted real designs for fabrication?
- Wafer volume: Is output sustained beyond demonstrations and engineering runs?
- Economics: Can Rapidus cover depreciation, labor, materials and yield losses?
- Packaging: Can it provide advanced packaging and chiplet integration at commercial scale?
- Delivery: Can it meet customer schedules and predictable cycle times?
Tom’s Hardware reported an initial potential production rate of roughly 6,000 12-inch wafers per month, with possible expansion toward approximately 25,000 wafers per month. Those figures should be treated as secondary reporting or potential capacity, not as a confirmed Rapidus production commitment. The report also discusses prospective customers and capacity.
How Rapidus compares with TSMC, Samsung and Intel
Rapidus is entering a market dominated by companies with deeper manufacturing histories and broader customer ecosystems.
| Company | Competitive position | Rapidus’s challenge |
|---|---|---|
| TSMC | Large advanced-node customer base, established production and extensive design enablement | Matching its yields, capacity, IP, packaging and predictable delivery |
| Samsung Foundry | Early GAA adoption and significant semiconductor manufacturing scale | Competing with an incumbent that already operates advanced processes |
| Intel Foundry | Leading-edge process ambitions, substantial manufacturing expertise and capacity in the United States and Europe | Building trust as a new commercial foundry while scaling its own process |
| Rapidus | Japanese supply-chain support, IBM collaboration, customer engineering and single-wafer development strategy | Proving yield, ecosystem depth, cost and dependable volume |
The competition is not simply about which company can demonstrate a transistor first. TSMC’s Open Innovation Platform, for example, includes EDA tools, silicon-proven intellectual property, design services and advanced packaging support. A new foundry must build comparable support or target customers whose needs are not fully served by existing suppliers. Tom’s Hardware has reported on Rapidus’s proposed pricing and ecosystem challenge.
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Rapidus has identified artificial intelligence, robotics, edge computing, high-performance computing, strategic Japanese systems and advanced chiplet designs as possible application areas.
In February 2026, the company was reported to be in discussions with more than 60 prospective customers. “In discussions” does not mean that those companies have signed production contracts, completed tape-outs or committed revenue-generating orders.
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Tom’s Hardware also reported a possible wafer price of ¥3 million to ¥3.5 million—approximately $18,550 to $21,635 at the exchange rate cited in that report—for 2-nm-class wafers at launch. These are reported or proposed figures, not confirmed final market prices. A lower quoted wafer price would not necessarily mean lower total chip costs if yields, packaging, design work or delivery reliability were less competitive.
Rapidus’s milestone timeline
- August 10, 2022: Rapidus was founded.
- December 2022: Rapidus and IBM announced their strategic partnership.
- September 2023: IIM-1 groundbreaking took place.
- December 2024: An ASML EUV system was installed.
- April 2025: The IIM-1 pilot line commenced operation.
- July 18, 2025: Rapidus confirmed electrical operation of 2-nm GAA transistor prototypes.
- February 2026: Rapidus announced ¥267.6 billion in public and private funding.
- 2027: Rapidus’s stated target for mass production.
The timeline shows that Rapidus has moved beyond a construction announcement. It does not yet show that the company has reached the manufacturing scale required to compete with established foundries.
What investors and industry watchers should monitor
The most useful future announcements will be specific rather than promotional. Watch for:
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- Named customer tape-outs and completed qualification programs.
- Published yield, defect-density or reliability data.
- Sustained wafer output rather than isolated prototype runs.
- Evidence that EUV tools and other equipment are operating at commercially useful availability.
- Advanced-packaging capacity for chiplets and 3D-integrated products.
- Additional financing requirements and the terms of any further public support.
- Actual customer pricing, delivery schedules and repeat orders.
These measures matter more than the existence of a new building, a funding headline or a working transistor demonstration.
Bottom line
Rapidus has already opened its 2-nm pilot line at IIM-1 and has reported functioning 2-nm GAA transistor prototypes. Japan therefore has reached a genuine pilot-stage milestone in its attempt to re-enter leading-edge logic manufacturing.
But pilot operation is not high-volume production. The 2027 mass-production date remains a target whose success will depend on yield, customer qualification, packaging, cost, financing and reliable delivery. Rapidus has demonstrated credible technical progress; it has not yet demonstrated that it can operate a commercially competitive foundry at scale.
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