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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteJapan’s Advanced SoC Design Talent Incubation Program (ADIP) is designed to train semiconductor engineers through a sequence that includes three months of pre-training in Tokyo and, for its advanced track, 12 to 18 months of on-the-job training at a Tenstorrent office in the United States. Tenstorrent announced a plan in November 2024 to host up to 200 Japanese silicon engineers over five years; that figure is a target, not a verified count of participants who have completed training.
Who runs the program, and what is it for?
ADIP is a NEDO-commissioned initiative led by the Leading-edge Semiconductor Technology Center (LSTC) and Tenstorrent. Its stated aim is to develop practical semiconductor design engineers and architects. The program has entry, intermediate, and advanced course levels; the U.S. Tenstorrent on-the-job training (OJT) is described as part of the advanced track. ADIP’s official overview
The initiative builds on a separate technical collaboration. In February 2024, Tenstorrent announced that it and LSTC had been selected to work on RISC-V and chiplet technology for Japan’s planned edge 2nm AI accelerator. That announcement provides context for the partnership, but it is distinct from the later engineer-training plan. Tenstorrent’s February 2024 announcement
What training is described?
Tenstorrent’s current published ADIP description sets out a Tokyo-to-U.S. sequence for the advanced course. It names RISC-V CPU design, AI accelerators, and chiplet implementation among the technical areas. The description does not establish that every participant works on every area. Tenstorrent’s ADIP program page
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
- Pre-training in Tokyo: Three months of preparation before the U.S. placement.
- U.S. OJT: Between 12 and 18 months of on-the-job development at a Tenstorrent office.
The 2024 announcement used a somewhat different list of technologies, naming RISC-V Ascalon, Tensix IP, and AI/HPC software. Those were planned focus areas in the announcement, not a guarantee that all trainees would receive identical assignments. Tenstorrent’s November 2024 announcement
How large is the plan, and what has been confirmed?
Tenstorrent’s November 5, 2024 announcement said it could host up to 200 Japanese silicon engineers at U.S. sites over five years and projected that the first official cohort would begin in April 2025. In an April 2026 profile, JETRO described a company target of developing 200 design engineers by 2029 through U.S. OJT. These are planned scale and target figures, not reported completion totals. JETRO’s April 2026 profile
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- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
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| Source and date | What it says | How to interpret it |
|---|---|---|
| Tenstorrent, November 5, 2024 | Up to 200 Japanese silicon engineers over five years; first official cohort projected for April 2025 | Original program plan and projected start, not a verified enrollment or graduation count |
| Tenstorrent’s current ADIP description, accessed October 4, 2026 | Three months of Tokyo pre-training followed by 12 to 18 months of U.S. OJT | Published training sequence for the program’s advanced track |
| JETRO, April 2026 | Target of developing 200 design engineers by 2029 through U.S. OJT | A later target, not evidence that 200 engineers have completed training |
The sources available as of October 4, 2026 do not give a verified number of people enrolled, graduated, or returned to their Japanese employers. They also do not specify full eligibility rules, selection criteria, or individual funding terms.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How does the program fit Japan’s semiconductor strategy?
The training effort is connected to Japan’s wider push to build domestic semiconductor design capability. LSTC chairman Tetsuro Higashi linked sending engineers to learn Tenstorrent’s technology with the partners’ work on an edge 2nm AI accelerator. His statement describes the intended strategic value; it does not establish a measured outcome of the training program. Tenstorrent’s announcement and Higashi’s remarks
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- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Tenstorrent said participants would return to their Japanese companies with knowledge of its technology and engineering practices. The published materials describe that as the intended transfer of expertise, but do not report how many participants have returned or what roles they hold afterward.
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- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
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- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
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