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Inside Intel’s D1D Fab: A Look Through the Looking Glass

Intel’s D1D is part of a nine-building Oregon wafer network. Here’s how automated transport and fab infrastructure work—and what Intel’s public information does not establish about D1D specifically.
From TheFinanceBase Team3 min to read
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Intel’s D1D is one building in a larger Oregon manufacturing network: it connects to D1X and seven other buildings through an automated wafer-transport system. Intel’s public figures describe shared infrastructure and its general fab design, but they do not spell out D1D’s precise current role or layout. Here is what can be said about the journey a wafer makes—and where the evidence stops being D1D-specific.

Where D1D fits in Intel’s Oregon network

D1D is part of Intel’s Oregon wafer-fabrication campus in Hillsboro, not a standalone factory whose operations can be described entirely from public figures. Intel says its wafer “superhighway” connects nine buildings, including D1D and D1X. The company describes D1D and D1X together as a little larger than 12 U.S. football fields; that comparison is for the two factories combined, not D1D alone. Intel’s global manufacturing press kit provides this network context.

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The distinction matters because Intel’s public materials often discuss D1D and D1X side by side, while identifying them as separate buildings. They do not provide a detailed, current division of process-development or production work between the two.

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How wafers move through the fab

Wafer transport is designed to keep people from having to carry batches between tools. Intel describes more than 27 miles of multilevel automated material-handling thoroughfares and 1,700 autonomous vehicles in the D1 factory system. Those are D1-system figures, not counts for D1D alone. Intel’s AMHS leader Mutaz Haddadin calls the system the “heartbeat and blood flow of the fab.”

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The vehicles move front-opening unified pods, or FOUPs. Intel says a FOUP can carry up to 25 wafers, and that a wafer’s fabrication journey takes weeks. A pod’s capacity is a maximum, not a claim that every trip carries 25 wafers. The figures describe the system and wafer journey generally; Intel does not publish a separate D1D-only vehicle or throughput count in these materials.

What the cleanroom—and the space below it—does

Intel’s general fab-tour material describes a cleanroom as a reconfigurable, “ballroom style” work area. Tools carry out wafer-processing steps, while a supporting utility network supplies them with electricity, ultrapure water, gases and chemicals from the subfab—the service space beneath the cleanroom. This helps explain the physical logic of a fab: the production floor is only one layer of a facility that also has to deliver tightly controlled utilities to equipment.

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That description comes from Intel’s general cleanroom resource, not a detailed D1D floor plan. It should not be read as proof of the exact configuration of D1D. Intel’s cleanroom explainer describes the general model.

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Keep D1X milestones separate from D1D

Some prominent Oregon fab milestones belong specifically to D1X. In an April 18, 2024 announcement, Intel Foundry said installation of an ASML-built High NA EUV lithography tool at D1X was complete and calibration had started. Intel described the tool as weighing 165 tons. That was the status reported in April 2024, not a current status update, and it is not evidence that the tool is in D1D. Intel Foundry’s 2024 announcement identifies D1X as the location.

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Likewise, Intel said in 2022 that the D1X Mod3 expansion added 270,000 square feet of cleanroom space. That figure is an expansion attributed to D1X, not a measurement of D1D. Intel’s 2022 expansion announcement describes the project.

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What public accounts reveal about fab operations

A historical Intel account offers a small window into the coordination behind production. In 2018, Intel described a daily 8:20 huddle in the D1X team room, where staff reviewed tool status, parts availability, forecasts and the need for expert support. The account characterized D1X operations as 24/7/365. It is a dated example from D1X, not a current description of D1D’s schedule or management routine. Intel Investor Relations’ 2018 account documents that example.

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Intel’s Oregon network is therefore easiest to picture in layers: buildings linked by automated transport, FOUPs carrying wafers between tools, and cleanroom equipment supported by utilities from below. The public material makes those systems legible, but it does not justify assigning every campus-wide number, D1X milestone or general fab feature specifically to D1D.

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