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Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →EUV lithography prints a pattern for one chip layer onto light-sensitive material on a silicon wafer. The scanner creates 13.5-nanometer light from tin droplets, reflects it from a patterned mask, and uses precision mirrors to project a reduced image onto the wafer. The wafer then goes through other fabrication steps, and the process is repeated across many layers; an EUV scanner alone does not make a finished chip.
What an EUV scanner does—and what it does not do
Lithography transfers a circuit pattern onto photoresist, a light-sensitive coating on the wafer. The pattern on the reticle, or mask, defines the features for that exposure. Later steps use the patterned resist to guide operations such as etching or implantation. A chip is built through many such steps and layers, not in a single scanner pass. ASML describes chipmaking as building transistor patterns layer by layer on a silicon wafer (ASML’s lithography principles).
EUV is used for selected intricate layers, while deep ultraviolet (DUV) lithography remains in use for other layers. ASML expects EUV and DUV to operate in parallel for years; EUV does not replace every other patterning method.
How EUV lithography works, step by step
- Coat and position the wafer. The wafer is prepared with photosensitive resist and loaded onto a precision stage. A reticle holds the pattern to be transferred for that layer.
- Generate EUV light. The source sends tin droplets through a laser interaction zone. Laser pulses flatten and vaporize each droplet into plasma, which emits EUV light at a wavelength of 13.5 nm. ASML’s current product overview says this process runs up to 50,000 times per second (ASML’s EUV lithography systems overview).
- Keep the optical path under vacuum. EUV is absorbed by air and most materials, so the path from source to wafer operates in high vacuum. Ordinary lenses that transmit visible light would absorb EUV, so the scanner relies on reflective optics instead.
- Reflect and reduce the reticle image. The reticle is reflective, as are the multilayer mirrors that guide the pattern through the optical column. In conventional NXE EUV systems, the optics reduce the reticle image by 4x before projecting it onto the wafer. Precise positioning of the optical components helps preserve the image.
- Expose and move across the wafer. The stage positions the wafer for an exposure, then moves it so the pattern can be printed across additional fields. ASML says its NXE stage checks and adjusts 20,000 times per second and positions the wafer within a quarter nanometer for each exposure; these are manufacturer specifications, not independent measurements.
- Develop the resist and continue fabrication. After exposure, resist processing reveals the pattern, which can guide subsequent fabrication operations. The wafer then moves through further processes and lithography exposures to build other layers.
Why EUV needs mirrors and a vacuum
The short wavelength helps the scanner project very small patterns, but it creates an unusual optical problem: EUV is absorbed readily by air and by materials that would ordinarily form lenses. ASML puts it plainly: “EUV light is absorbed by everything, even air” (ASML’s EUV systems page). A vacuum optical path and reflective multilayer mirrors are therefore essential parts of the system, not optional refinements.
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- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
What High-NA EUV changes
ASML’s EXE High-NA platform raises numerical aperture from 0.33 in NXE systems to 0.55, a change intended to improve resolution. Numerical aperture describes an optical system’s ability to collect light and resolve detail. ASML describes EXE as supporting advanced logic and memory manufacturing, but that positioning by itself does not establish a particular customer’s production status.
High-NA also changes how the reticle image is reduced. Rather than the conventional 4x reduction in both directions, EXE uses anamorphic optics: 4x in one direction and 8x in the other, while retaining the established reticle size. The resulting exposure field is half the size of NXE’s, so twice as many exposures are needed to pattern a wafer. Faster wafer and reticle stages are intended to offset that added exposure count (ASML’s January 25, 2024 High-NA explainer).
Rank #2
- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
That 2024 explainer forecast customer research and development followed by high-volume manufacturing in 2025–2026. It was a forecast made at that time, not confirmation that the transition occurred on schedule. ASML also describes EXE as offering “8 nm resolution”; that is a company-stated imaging capability, not a claim that every feature on a chip is 8 nm wide. Likewise, process-node labels such as “2 nm” are generation names, not literal measurements of every transistor feature.
How EUV compares with DUV
| Characteristic | EUV / NXE | DUV or High-NA / EXE |
|---|---|---|
| Wavelength | EUV: 13.5 nm, according to ASML’s product overview. | High-resolution DUV: 193 nm, according to ASML’s product overview. |
| Numerical aperture | NXE: 0.33. | EXE High-NA: 0.55, according to ASML’s lenses-and-mirrors explainer. |
| Reticle-image reduction | NXE: 4x. | EXE: anamorphic 4x in one direction and 8x in the other. |
| Exposure field | NXE’s field is the reference size. | EXE’s field is half the size, requiring twice as many wafer exposures; faster stages are intended to counter the added count. |
These figures describe different platforms and capabilities, not a complete comparison of manufacturing cost, yield, or performance. ASML’s lithography principles explain the broader role of lithography, while its EUV systems overview covers the EUV product family.
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Rank #3
- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
What the recent source-power figures mean
ASML’s current EUV product overview describes tin-droplet laser interactions running up to 50,000 times per second. Separately, its 2025 annual-report strategy page says its latest commercial sources repeat the process 60,000 times per second. Those figures come from different company pages and system contexts, so they should not be treated as interchangeable specifications.
The same 2025 strategy page reports that ASML demonstrated a 1,000-watt EUV light source in April 2025. That was a demonstration milestone, not a statement that standard commercial production sources operate at 1,000 watts (ASML’s 2025 annual-report strategy page).
Rank #4
- Multiple Diameter Options: Available in multiple diameters including 1, 2, 3, 4, 5, 6 and 8 inch silicon wafers
- Durable Substrate Design: Flat and solid silicon substrate supports cutting, polishing and controlled experimental handling
- Research and Educational Applications: Commonly used in laboratories, universities, research institutes and educational environments
- Precision Polished Wafer Surface: Manufactured with smooth and stable wafer surfaces, available in SSP (Single Side Polished) and DSP (Double Side Polished) configurations for sample preparation, handling, and laboratory processing.
- Wide Laboratory Applications: Commonly used in universities, research institutions, material science laboratories, and scientific training programs for silicon material studies and experimental demonstrations.
What these specifications do not establish
ASML’s published pages are primary sources for its own equipment architecture and company-reported capabilities. The figures above should be read in that context: they do not establish fab-level yields, total cost differences between EUV and DUV, or whether a specific manufacturer has moved a process into high-volume production. Nor does a scanner’s resolution figure specify the width of every feature in a finished chip.
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Best Value
- Durable Design: Crafted from high-quality, transparent plastic for long-lasting use and easy visibility of contents.
- Single Wafer Capacity: Accommodates one 12-inch silicon wafer, providing secure storage and transportation.
- Protective Features: Raised edges and secure locking mechanism help prevent wafer damage during handling.
- Compact Size: Lightweight and portable, making it convenient for lab use or transportation.
- Versatile Application: Suitable for various industries utilizing silicon wafers, such as semiconductor manufacturing.
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