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Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Flex Logix stopped selling its InferX X1 accelerator chip and board and shifted to licensing the underlying technology as semiconductor IP. The company’s stated reason was commercial scale: CEO Geoff Tate told EE Times in May 2023 that the market for chips and boards was relatively small, and that the customer volumes available to a startup were not attractive. InferX continues as technology intended for chipmakers and systems companies to integrate into their own systems-on-chip (SoCs), rather than as a product for ordinary buyers.
Why did Flex Logix stop selling the InferX chip?
The pivot was a change in business model, not an announcement that the InferX architecture had been abandoned. Flex Logix ended standalone InferX X1 chip and board sales and chose to license the technology instead. In May 2023, Tate told EE Times: “What we were finding was that the market for chips and boards was relatively small.” He said the company saw interest from automotive customers, but automotive was not a market a startup could readily sell into. Tate described the conclusion as licensing “everything that we built.”
The underlying commercial issue was volume. A company selling its own accelerator chip needs enough customers and unit sales to justify developing, manufacturing, and supporting that product. Flex Logix’s established eFPGA intellectual-property business offered another route: license technology to SoC designers who can incorporate it into their own chips. That lets a customer build around its own product and manufacturing plans, while Flex Logix pursues licensing rather than relying on sales of a standalone accelerator.
What InferX IP is—and what it is not
InferX is a reconfigurable accelerator architecture that combines tensor processing built from multiply-accumulate (MAC) operations with a reconfigurable, FPGA-style interconnect. Its intended distinction is to pair specialized computation with the ability to change how parts of the fabric are configured for different workloads. Flex Logix described the design in its April 2023 announcement as “80% hard-wired, but 100% reconfigurable.” That is the company’s characterization of the architecture, not a standardized measure of flexibility or a guarantee of performance.
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As licensed IP, InferX is a design component for a chip or system—not a retail accelerator card or a consumer device. The intended customers are chipmakers and systems companies designing SoCs. The IP can be integrated into a customer’s own silicon, rather than used only as an external accelerator connected to a host system.
How the AI and DSP software paths differ
Flex Logix describes related hardware for AI inference and digital signal processing (DSP), but the software path depends on the job. The AI flow is built around preparing and compiling neural-network models. The DSP path supports configurable signal-processing operations.
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AI inference
The AI software path includes model quantization, graph and operator compilation, and fabric configuration. Flex Logix says the tools can configure the hardware to reduce traffic to external memory. The practical result for an SoC designer depends on the particular model, configuration, implementation, and system; the available figures should not be read as a universal speed or efficiency result.
Digital signal processing
The DSP path is aimed at operations such as fast Fourier transforms (FFTs), finite impulse response (FIR) filtering, and matrix processing. Reconfiguration can support different functions or FFT sizes. In a March 2024 announcement, Flex Logix described an InferX DSP tensor processor with 128 INT16 MACs, delivered as soft IP for EFLX eFPGA implementations from 40 nm to 7 nm. Soft IP is a configurable design implementation rather than a finished, fixed chip.
What the reported performance figures mean
InferX figures are tied to particular configurations and process nodes. They are not interchangeable measures of one finished product, and the figures below do not establish performance in every customer design.
| Reported figure | Configuration and qualification |
|---|---|
| 4 TOPS INT16 per tile; 1 TOPS for complex INT16 per tile | EE Times reported these figures in 2023 for a TSMC N5 implementation running at 1 GHz. |
| 175 YOLOv5-S inferences per second | EE Times reported this 2023 result using two compute tiles in TSMC N7. It is a model- and configuration-specific figure, not a general rate for all AI workloads. |
| 16 INT8 TOPS at 1 GHz and approximately 1 W per tile | A September 2026 TechInsights report described this as a Flex Logix target for a 5 nm process. It is a reported target, not an independent benchmark result. |
TOPS means trillions of operations per second. Comparisons based on TOPS alone can mislead: precision, workload, process node, clock, tile count, power measurement conditions, and how the accelerator is integrated all matter. The figures above come from different reports and configurations, so they should not be combined into a direct ranking against a GPU, FPGA, or another accelerator.
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How to compare InferX with GPUs, FPGAs, and other accelerators
There is no single apples-to-apples comparison established by the reported figures. A chip designer evaluating InferX would need to compare specific implementations and workloads across several dimensions:
- Integration: InferX IP is intended to be incorporated into an SoC; a standalone accelerator is a separate chip or board.
- Workload: InferX is described for AI inference and DSP, with different software paths for each. A comparison should use the same model or signal-processing task.
- Reconfigurability: InferX combines specialized MAC/tensor hardware with reconfigurable interconnect. A fixed-function accelerator and a conventional FPGA make different trade-offs in specialization and flexibility.
- Efficiency: Compare performance per watt and per area only for a specified process node, precision, operating conditions, and workload—not from peak TOPS alone.
- Software: Evaluate AI quantization and compilation tools separately from DSP programming support and available operations.
- Commercial scale: For a licensed block, design-win prospects, customer adoption, integration effort, and licensing terms matter alongside the silicon’s technical characteristics.
Who can license InferX, and what is the foundry alliance?
Flex Logix’s stated audience is chip and SoC designers, not individual consumers. A company developing a semiconductor product could assess whether the AI or DSP IP fits its architecture and implementation requirements. The public material summarized here does not establish license pricing, contract terms, or a general-purpose signup process.
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In February 2024, Flex Logix joined Intel Foundry’s Accelerator IP Alliance, an ecosystem intended to connect IP providers with foundry customers. The alliance is a route to reach potential design customers; its announcement by itself does not establish a specific InferX customer, design win, production deployment, or commercial result.
InferX timeline
| Date | Milestone |
|---|---|
| April 24, 2023 | Flex Logix announced InferX IP and software for DSP and AI inference. |
| May 8, 2023 | EE Times reported that Flex Logix had stopped selling InferX X1 chips and would license the architecture. |
| February 12, 2024 | Flex Logix joined Intel Foundry’s Accelerator IP Alliance. |
| March 6, 2024 | Flex Logix announced InferX DSP development for EFLX eFPGA implementations from 40 nm to 7 nm. |
| September 8, 2026 | TechInsights reported that Flex Logix had ceased chip-building operations and was offering InferX tiles as IP. |
For readers following semiconductor businesses, the central point is that InferX’s commercial path is now licensing and integration into other companies’ SoCs, rather than sales of a Flex Logix-branded X1 chip or board. The available reports establish the strategic shift and describe intended capabilities; they do not, on their own, establish how widely the IP has been adopted or what revenue it will generate.
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