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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsEuclyd is proposing—not yet demonstrably shipping—a radically dense AI-inference system. The Eindhoven, Netherlands, startup says its CRAFTWERK system-in-package (SiP) could combine 16,384 custom SIMD processors with 1 TB of proprietary “Ultra Bandwidth Memory” and up to 8,000 TB/s of memory bandwidth. Its headline performance figures are company projections, not independently verified production benchmarks.
The concept targets a real problem: the energy, latency and infrastructure cost of repeatedly moving large AI-model data between processors, memory and separate accelerator devices. Whether Euclyd can turn that architecture into reliable, manufacturable and economically competitive hardware remains unproven.
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What Euclyd is proposing
Euclyd emerged from stealth in September 2025 as a Dutch AI-chip startup headquartered in Eindhoven. The company was founded by Bernardo Kastrup; Atul Sinha has been identified as a founder and adviser. Early backers named by EE Times include former ASML chief executive Peter Wennink, microprocessor pioneer Federico Faggin, and Elastic founder Steven Schuurman.
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Those names add credibility to the company’s financing and semiconductor connections, but they do not independently validate CRAFTWERK’s performance claims.
Euclyd’s central argument is that large-scale AI inference is increasingly limited by data movement. SRAM is fast but expensive and capacity-constrained. HBM provides substantially more capacity and bandwidth, but may still require models to be divided across multiple devices. Distributed accelerator systems then add networking, synchronization and power overhead.
CRAFTWERK attempts to address those constraints by placing compute chiplets and custom memory in one very large package.
CRAFTWERK SiP explained
A system-in-package is not simply one conventional monolithic processor. It can combine multiple pieces of silicon—such as compute chiplets, memory and interconnect circuitry—inside one package.
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Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →| Reported element | Euclyd’s proposed specification |
|---|---|
| Processing elements | 16,384 custom SIMD processors |
| Compute | Up to 8 PFLOPS FP16 or 32 PFLOPS FP4 |
| Memory | Up to 1 TB of custom DRAM-based Ultra Bandwidth Memory |
| Memory bandwidth | Up to 8,000 TB/s, or approximately 8 PB/s |
| Package or interposer scale | Approximately 100 mm × 100 mm |
| Single-SiP thermal target | About 3 kW TDP |
These are reported design targets and company claims. PFLOPS describes peak mathematical capability, not the application-level speed users necessarily receive. Likewise, a peak bandwidth figure does not establish sustained bandwidth under real model access patterns, contention or software overhead.
What is Ultra Bandwidth Memory?
Euclyd calls its custom memory design Ultra Bandwidth Memory, or UBM. The company says it can provide 1 TB of capacity and up to 8,000 TB/s of bandwidth while remaining closely coupled to the compute chiplets.
UBM is not a broadly established industry memory standard in the way HBM is. Public information does not establish its channel structure, signaling method, error correction, refresh overhead, thermal characteristics, manufacturing partner or usable application bandwidth. It would therefore be inaccurate to declare UBM categorically faster than HBM without specifying the generation, interface, operating rate and whether the comparison uses theoretical or sustained bandwidth.
Bandwidth is only one part of inference performance. Results also depend on model architecture, sparsity, quantization, cache behavior, compiler scheduling, attention implementation, KV-cache traffic and workload concurrency.
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The performance claims
Euclyd says a single CRAFTWERK SiP could produce 20,000 tokens per second when running Meta’s Llama 4 Maverick 400B model at roughly 3 kW TDP. Its proposed CRAFTWERK STATION CWS 32 rack would combine 32 SiPs and 16 host CPUs in a liquid-cooled system rated at approximately 125 kW, with a projected 7.68 million tokens per second in a multi-user scenario.
For context, figures cited by Euclyd and reported by EE Times put a single-user Llama 4 Maverick 400B result at 1,038 tokens per second for an Nvidia DGX B200 and 2,554 tokens per second for Cerebras hardware. Those comparisons are not automatically like-for-like. A proper comparison would need to specify:
- Model version, parameterization and precision;
- Prompt and output lengths;
- Quantization, sparsity and speculative decoding;
- Batch size and user concurrency;
- Time to first token versus output-token rate;
- Whether the result is measured, simulated or vendor-modeled;
- Whether host CPUs, networking, cooling and power-conversion losses are included.
The correct description is therefore “Euclyd’s projected throughput,” not “Euclyd delivers 20,000 tokens per second.”
Why the package creates engineering risk
A roughly 100 mm × 100 mm interposer suggests an unusually large integration area, short compute-to-memory connections and potentially high package-level bandwidth. It also raises difficult manufacturing questions involving interposer fabrication, reticle limits, warpage, thermal expansion, defect density, known-good-die testing, assembly yield and serviceability.
The terminology matters: an approximate interposer dimension is not necessarily the overall package dimension, the active silicon area or proof that a production package has been manufactured. Advanced 2.5D and 3D packaging can deliver impressive density, but the economics depend heavily on yield and access to specialized packaging capacity.
Thermal density is another obstacle. A 3 kW SiP is far beyond the power envelope of an ordinary server accelerator card and would likely require direct liquid cooling and specialized power delivery. A 125 kW rack could suit a hyperscaler designed for liquid-cooled infrastructure, but it may be impractical for a conventional enterprise server room. Operators would need to account for electrical distribution, cooling capacity, floor loading, plumbing, maintenance and power-conversion losses.
The software question
Euclyd says CRAFTWERK will be fully programmable and intended to support transformer, multimodal, reasoning, recurrent, state-space and diffusion models. It also says it is designing its own processors rather than adopting an Arm or RISC-V CPU architecture.
That may give Euclyd architectural control, but it does not eliminate the software challenge. Customers would need answers to practical questions such as:
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- Are common operators automatically lowered to the hardware?
- Is CUDA compatibility available, or is model porting required?
- How are quantization, sparsity, dynamic shapes and collective operations handled?
- What happens when a model uses an unsupported operator?
- Are a simulator, profiler, debugger and public SDK available?
The researched public material does not verify those capabilities. For an inference platform, compiler maturity, operator coverage and debugging tools can matter as much as raw silicon specifications.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Manufacturing and commercial status
Euclyd announced a development collaboration with Korean semiconductor design house ADTechnology in November 2025 to help bring CRAFTWERK to silicon. In April 2026, reporting said Euclyd was seeking approximately €100 million to expand manufacturing and move toward customer deliveries.
That reported figure is a fundraising effort—not evidence that the round has closed and not a product price. As of the latest status covered by the supplied reporting before August 18, 2026, there was no independently verified evidence of broad commercial deployment or scaled customer benchmarking. The same April report cautioned that the company’s efficiency advantage had not yet been demonstrated at scale in real-world deployments. Sources include NL Times and ADTechnology’s announcement.
For buyers, the distinction between an announced architecture, a design target, working silicon, a prototype benchmark and a production customer deployment is essential. Euclyd’s public claims currently belong primarily to the first two categories.
What investors and infrastructure buyers should verify
- Working silicon: Has CRAFTWERK taped out, and has a complete package been tested?
- Memory implementation: Is the 1 TB UBM configuration in hardware, and is 8,000 TB/s peak or sustained?
- Manufacturing: Which foundry and packaging providers are involved, and what are expected yields?
- Software: Can customers run mainstream models without extensive hand-porting?
- Benchmarks: Are results independently measured under reproducible model, precision and concurrency conditions?
- Economics: Do cost per token and energy per token include depreciation, cooling, staffing, software and utilization?
- Operations: Can the customer support a 3 kW package and 125 kW rack?
Alternatives available today
Euclyd does not appear in the supplied material as a generally available product with public pricing or a standard procurement channel. Organizations needing inference infrastructure now may instead evaluate established Nvidia data-center hardware (Nvidia), cloud-based AWS Inferentia (AWS) or Google Cloud TPU (Google Cloud).
Specialized alternatives include Cerebras systems (Cerebras) and managed inference through services such as GroqCloud (Groq). Each involves trade-offs in software compatibility, availability, cloud dependence, workload fit and total cost. Euclyd is better treated as a platform to monitor than as hardware that most organizations can currently order.
Bottom line
Euclyd is addressing a genuine inference bottleneck: moving large-model data efficiently between compute and memory. Its proposed CRAFTWERK design is notable for its scale, custom memory and tightly integrated packaging. But the 20,000-token-per-second SiP claim, 8,000 TB/s bandwidth figure and 7.68-million-token-per-second rack projection remain company-provided targets. The investment case and procurement case depend on proof of working silicon, manufacturable packaging, usable software, independent benchmarks and competitive total cost of ownership.
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