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Codasip did begin an expedited process to sell the company on July 1, 2025, but the latest public record points to a strategic carve-up rather than a confirmed whole-company takeover. On April 8, 2026, Codasip said it had divested its low-end RISC-V processor-design business to an unnamed public U.S. semiconductor company while retaining a focus on CHERI-enabled, cyber-resilient architectures. Specialist publication XPU identified the buyer as onsemi, but Codasip has not officially named it.
The result is significant for Europe’s technology sovereignty: the continent may retain Codasip’s security-focused work, yet conventional processor IP, tools and possibly engineering talent have moved closer to a U.S.-controlled semiconductor business. The effect on the EU-funded high-performance DARE project remains unresolved.
What was actually put up for sale?
Codasip’s July 2025 announcement was broader than a normal product sale. Its board said it would consider a whole-company acquisition, a partial acquisition or separate asset transactions, with an intended completion window of three months. The company described four separable areas:
- Codasip Studio, its processor-design and customization platform.
- Standard application and embedded RISC-V processor IP.
- CHERI-based application and embedded processors and software.
- High-performance application processors under development, including work connected with European funding.
Codasip said it had received more than €119 million in EU and national grants and equity funding, estimated possible follow-on grant phases at about €210 million and identified potential additional financing of at least €51 million. Those latter figures were projections, not cash already received. It also reported approximately 250 employees, including 57% hardware engineers and 30% software engineers, with research and development in Europe at that time. See the July 1, 2025 announcement.
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Timeline: from sale process to restructuring
- March 6, 2025: Codasip was selected to design a high-end general-purpose RISC-V processor for the EU-funded DARE project, described by Codasip as a €240 million initiative. The announcement is available at Codasip’s DARE release.
- July 1, 2025: The board launched an expedited process covering a possible whole-company sale, partial sale or asset deals.
- July–October 2025: The announced three-month target window passed without a closing announcement identified in Codasip’s official newsroom.
- November 19, 2025: Codasip announced a strategic licensing agreement with EnSilica involving a CHERI-enabled embedded CPU from its 700 family. The release is listed in the company’s newsroom.
- April 8, 2026: Codasip announced a “corporate portfolio realignment,” divesting its low-end RISC-V processor-design business and granting the buyer a broad Codasip Studio license. The company said the buyer was a public U.S. semiconductor company and that the transaction was planned to close in approximately one month. Read the April 8 announcement.
- April 27, 2026: XPU reported that the buyer was onsemi and characterized the event as a restructuring after roughly a year-long sale process. That identification remains secondary reporting: XPU’s report.
- June 29, 2026: European Commission CORDIS reporting said DARE specifications for two processors had been completed, while verified designs were still pending: CORDIS project reporting.
What was sold, and what appears to remain?
| Business or asset | Publicly indicated status |
|---|---|
| Low-end RISC-V processor-design business | Divested; the official buyer name was not disclosed. |
| Codasip Studio | A broad license was granted to the buyer as part of the divestiture. |
| CHERI-enabled processors and security work | Retained as the center of Codasip’s stated strategic direction. |
| CHERI system-on-chips and FPGAs | Included in the cyber-resilient architecture focus announced in April 2026. |
| High-performance RISC-V and DARE-related work | Its ownership, staffing and licensing treatment have not been fully clarified publicly. |
| Entire Codasip corporate entity | No verified evidence in the cited releases of a completed whole-company sale. |
Why the buyer’s identity matters
Codasip’s official wording establishes only that a public U.S. semiconductor company acquired the low-end business. XPU’s identification of onsemi is useful but should not be treated as primary confirmation.
If the reported buyer is onsemi, possible commercial motives include gaining processor-design capability, integrating cores into custom silicon, strengthening automotive and industrial offerings, and acquiring engineering talent and Studio know-how. These are analytical possibilities, not statements from onsemi or Codasip. The strategic effect depends on which cores, tools, patents, employees, customer contracts and roadmap rights actually transferred.
What “European RISC-V sovereignty” should mean
RISC-V is an open instruction-set architecture governed through an international ecosystem. Europe does not lose ownership of the ISA because a European company sells a business. But openness at the instruction-set level does not guarantee European control of the commercial layers built on it.
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Ownership and roadmap control
Processor implementations, proprietary extensions, verification environments, compilers, support contracts and future security updates can remain under one company’s control even when the underlying ISA is open.
Engineering talent
Codasip described a predominantly European engineering organization in 2025. Whether engineers moved to the buyer, remained with Codasip or became available to other European companies is not established in the public announcements.
Funding and project leverage
EU and national grants can create public-interest obligations concerning foreground intellectual property, access, licensing and continuity. Awarded funds, projected follow-on phases and potential consortium financing are not interchangeable, and the applicable transfer conditions have not been fully published for this transaction.
Rank #3
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- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
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Customer dependence
European customers may continue to access the RISC-V ISA while becoming dependent on a non-European owner for a particular core, toolchain, certification path, support organization or security-maintenance schedule.
The DARE complication
DARE—Digital Autonomy with RISC-V in Europe—is more than a private commercial program. Codasip was selected to design a high-end general-purpose processor within the initiative, which Codasip described as a €240 million first phase intended to build a European supercomputing stack using high-performance and energy-efficient RISC-V processors and accelerators.
CORDIS reported on June 29, 2026 that specifications for two processors were complete but verified designs were still pending. That means DARE represents substantial public investment and strategic capability, not a finished European processor that can simply be counted as delivered.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
The crucial unanswered questions are whether DARE-related designs, staff or contractual rights were included in the divestiture; whether grant agreements restrict transfer or licensing; and which entity is responsible for delivery, maintenance and public-access commitments. The available announcements do not settle those issues.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why CHERI changes the interpretation
Codasip says it is pivoting toward CHERI—Capability Hardware Enhanced RISC Instructions—and cyber-resilient semiconductor architectures, including CHERI processors, system-on-chips and FPGA implementations.
CHERI is designed to enforce stronger memory-safety and compartmentalization properties in hardware rather than relying only on software patches. That can be strategically relevant to government systems, critical infrastructure, automotive electronics, industrial controls and other platforms where a memory-safety failure can have serious consequences.
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The trade-off is commercial scale. CHERI remains more specialized and less broadly deployed than conventional processor IP. Customers need compatible compilers, operating systems, debuggers, verification flows, silicon and long-term support. Codasip’s July 2025 release attributed “70% or more” of CVEs to memory-safety violations; that figure should be understood as a company claim rather than a settled universal statistic.
Codasip may therefore be exchanging breadth in mainstream RISC-V IP for differentiation in a security-focused niche. Retaining that capability could preserve an important European asset, but its strategic value will depend on adoption, production deployments and durable commercial support.
How to judge whether this is a sovereignty setback
- Asset ownership: Identify whether only low-end cores moved, or whether high-performance designs, patents, tools and teams also transferred.
- Roadmap control: Establish who controls features, security fixes, licensing and export decisions.
- Personnel: Track where the relevant engineers and program managers now work.
- Grant conditions: Review restrictions on IP transfer, sublicensing, access and project continuity.
- Customer continuity: Check whether existing European customers retain comparable prices, modification rights and support.
- Open-versus-proprietary boundaries: Separate what RISC-V standards provide from what each vendor owns.
- Security capability: Determine whether CHERI work remains European-controlled and commercially viable.
- Alternatives: Assess whether other European firms, universities, OpenHW projects or public programs can replace lost capability.
What remains unknown
- The legal name of the buyer and the exact transaction structure.
- The confirmed closing date and purchase price.
- Which employees, customer contracts, patents and Studio components transferred.
- The treatment of DARE-related IP, grants and delivery obligations.
- Future licensing and support arrangements for existing Codasip customers.
- Whether Codasip’s remaining operations are still controlled and staffed primarily from Europe.
Bottom line for policymakers and customers
Europe did not lose the RISC-V instruction set, and the public record does not prove that Codasip as a whole was acquired. It does show a sale process followed by the divestiture of a significant conventional RISC-V business to a U.S. semiconductor buyer whose identity Codasip has not officially disclosed.
Codasip’s retained CHERI and cyber-resilience strategy may preserve a strategically valuable European capability. But the final sovereignty judgment depends on the ownership of high-performance work, the fate of DARE obligations, the location of engineering talent and the practical licensing terms available to European customers.
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