On March 26, 2002, Shanghai-based Advanced Semiconductor Manufacturing Corp. (ASMC) announced plans to break ground that month on a 200-mm, or 8-inch, wafer fab, with production targeted for 2003. The proposed facility was meant to expand ASMC’s foundry business in analog, power-management and other specialty chips—not to put the company in direct competition with leading-edge digital foundries. Later reporting and company filings show that the project advanced from announcement to construction, equipment procurement and wafer manufacturing.
What ASMC announced in March 2002
ASMC said it planned to begin construction in Shanghai during March 2002 and expected the new fab to start production in 2003. The contemporary report described the company as a joint venture involving Chinese government interests and Royal Philips Electronics. At the time, ASMC was an established Shanghai chip manufacturer with existing production lines; the new fab was an expansion, not the start of its semiconductor operations. EE Times reported the announcement on March 26, 2002.
ASMC’s starting point—and a capacity discrepancy
Before the 200-mm project, ASMC operated a 5-inch bipolar line and a 6-inch CMOS line. The contemporary accounts do not agree on their combined capacity. EE Times and EDN reported 480,000 wafers per month, while a U.S. General Accounting Office (GAO) report prepared around February 2002 listed approximately 40,000 wafers per month. The difference is substantial, and the available accounts do not explain whether it reflects a reporting, unit or other discrepancy; neither figure should be treated as settled without qualification.
- EE Times reported a combined capacity of 480,000 wafers per month.
- EDN repeated that figure and described a class-10 bipolar facility and class-1 CMOS cleanroom.
- The GAO report listed approximately 40,000 wafers per month for ASMC’s 5- and 6-inch operation.
The GAO’s February 2002 snapshot also listed ASMC as founded in 1988, with an approximate minimum feature size of 0.6 micron in its existing operation and about 62% Chinese ownership. Those are historical figures reported in that survey, not claims about the company’s permanent ownership or capabilities.
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An 8-inch wafer has substantially more surface area than a 5- or 6-inch wafer, so it can yield more dies per wafer. When process yield and equipment utilization are adequate, that can lower manufacturing cost per die. A larger format does not guarantee lower costs: a fab has significant fixed expenses, and its economics depend on usable yield, tool utilization, qualified processes and customer demand. Some mature products can also remain economical on older equipment.
Two different technical measures matter here. “200 mm” or “8-inch” refers to wafer diameter; it does not describe transistor size. A September 2002 follow-up identified the new fab’s process as 0.35 micron, or 350 nm. That was a mature process by 2002 standards, suited to products that did not require the smallest geometries. The distinction helps explain why the project was a meaningful manufacturing upgrade without being a leading-edge logic facility. The September report supplied the 0.35-micron specification.
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The intended market: analog, power and specialty chips
ASMC said it did not plan to compete directly with major foundries in Taiwan and Singapore. Instead, it expected to focus on analog chips, power ICs and other specialty products. Such work can depend on reliable, qualified processes and customer-specific manufacturing as much as on shrinking feature sizes. The new wafer format therefore fit a capacity and efficiency strategy for mature-process products rather than a race to make the most advanced processors.
California Micro Devices provided a concrete example of that strategy. In early March 2002, it agreed to use ASMC for manufacturing analog semiconductors and application-specific integrated passive (ASIP) devices. The arrangement involved transferring California Micro Devices’ thin-film manufacturing processes to ASMC and supported a “fab-lite” model: California Micro Devices would rely more on outside production rather than manufacture everything itself. The agreement linked the Shanghai fab’s specialty focus to a customer and a process transfer, rather than leaving the expansion as a general capacity proposal. Contemporary coverage is available from EDN and EE Times; the SEC-filed manufacturing agreement provides the contract record.
Construction, equipment and production milestones
The March announcement was an intention, not proof that the fab was already built. A September 2002 update reported that ASMC had broken ground. It said equipment move-in was planned for March 2003 and initial IC production was expected in June 2003; the first phase was reported at 5,000 wafers per month. These were plans and a first-phase figure, not evidence that production began on the planned date or that 5,000 wafers per month was the facility’s final capacity.
Subsequent records show further progress. In 2003, equipment supplier ASML announced that ASMC had ordered three lithography systems for the new 200-mm fab: two PAS 5500/250 systems and one PAS 5500/300. ASML’s announcement is evidence of equipment procurement for the ramp.
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A later California Micro Devices filing said ASMC began manufacturing wafers for the company in the fourth quarter of 2003 at a new 200-mm, QS9000-certified foundry in Shanghai. The filing described guaranteed wafer-start capacity for specified specialty processes: at least 5,000 starts per month from September 2003 through March 2004, then 10,000 per month from April 2004 through December 2006. These were contractual commitments for that customer and those processes, not a statement of the fab’s total output or utilization. The filing records both the commitments and the fourth-quarter manufacturing start.
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ASMC’s project combined Chinese participation with international commercial and technology relationships. The 2002 reports described a venture involving Chinese government interests and Philips. A later industry account said Philips owned 38% of ASMC; that percentage is attributable to that account, rather than an independently verified figure here. The GAO’s February 2002 table, meanwhile, estimated ASMC as 62% Chinese-owned. These descriptions reflect particular historical sources and dates, not a single ownership figure that can be assumed to hold across the period. China Economic Review reported the 38% Philips figure.
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The project also belonged to a wider wave of semiconductor investment in China. The GAO’s 2002 survey placed ASMC alongside planned or operating 8-inch facilities associated with Motorola, Shanghai Hua Hong NEC, Grace Semiconductor and SMIC. That context shows the Shanghai fab as part of a broader expansion of manufacturing capacity, while ASMC’s reported 0.35-micron process and specialty focus distinguish its role from a claim to lead-edge production. The survey is available as a GAO PDF.
What the project represented
ASMC’s 200-mm fab plan marked a shift toward larger-wafer manufacturing and an expansion of China’s specialty foundry capacity. Its customer agreement, equipment order and later reported wafer manufacturing indicate that the project moved beyond a groundbreaking announcement. The evidence supports an account of a mature-process facility developed through Chinese and international partnerships; it does not establish eventual utilization or profitability, nor does it make the fab a leading-edge logic rival or proof of complete domestic technological independence.
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