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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchCadence completed its acquisition of Arm’s Artisan foundation-IP business on August 26, 2025, four months after announcing the deal. Artisan adds advanced-node standard-cell libraries, memory compilers and general-purpose I/O libraries to Cadence’s portfolio—building blocks for SoCs and chiplet dies, not a turnkey chiplet or 3D-IC platform. The purchase price was not disclosed. Cadence announced the completion on August 27, 2025.
What Cadence acquired from Arm
The April 16, 2025 agreement covered Arm’s Artisan foundation-IP business. Cadence described the assets as standard-cell libraries, memory compilers and general-purpose I/O (GPIO) libraries optimized for advanced process nodes at leading foundries. The transaction was structured as an asset purchase, with a concurrent technology-license agreement to be signed at closing, subject to existing rights. It also included associated engineering expertise and personnel and relationships tied to advanced foundry processes. Cadence’s announcement did not disclose the purchase price.
This was not a purchase of Arm’s CPU architecture, CPU cores or entire IP portfolio. Arm retained those businesses. It sold the Artisan foundation-IP operation and said the transaction would keep physical IP needed to deploy Arm technology available to the ecosystem through Cadence. Arm’s filing records the sale’s completion on August 26, 2025.
What foundation IP does
Foundation IP supplies the process-specific physical elements used to implement a chip. It is distinct from both higher-level functional IP and the software used to design a chip.
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- Standard-cell libraries provide characterized logic and physical building blocks used to implement a design and meet power, performance and area targets.
- Memory compilers generate embedded-memory macros suited to a given process and design specification.
- GPIO libraries provide general-purpose input/output cells at the die boundary; requirements can differ by voltage domain, signaling standard and application.
- Interface and application IP includes functional blocks such as PCIe, SerDes, HBM, DDR, Ethernet and security. These are not interchangeable with foundation libraries.
- EDA software helps teams design, verify, analyze and implement the chip; it is not itself silicon IP.
Foundation IP must be characterized and validated for particular foundry processes and nodes. A library made for one process cannot simply be assumed to transfer to another. Memory design also has to account for factors such as timing, power, density, repair and yield.
Why foundation IP matters to chiplets—and what it does not do
A chiplet product still consists of silicon dies. Each die needs logic cells, memory structures, I/O, clocking, power design and physical-design collateral. Multi-die systems may combine dies made on different process nodes, increasing the importance of process-qualified IP for each one. Reusable, foundry-aligned libraries can help reduce design risk and support the path to tapeout.
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Cadence tied the acquisition to its chiplet offerings and a strategy combining IP, libraries, tools and design services. That is the company’s stated rationale, not proof that buying Artisan automatically accelerates every chiplet project. Foundation IP supports the silicon on a die; it does not provide a complete die-to-die interconnect, package, or 3D-IC solution.
Design teams still have to address die-to-die PHYs and protocols, package design, power and signal integrity, thermal and mechanical behavior, verification, test, assembly and manufacturing. A chiplet’s physical IP must work within the constraints of its interface and package. Qualified libraries cannot guarantee a design will meet yield, thermal, cost or reliability targets.
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How the deal fits Cadence’s portfolio
Artisan fills a different layer from Cadence’s interface, memory-interface, SerDes and embedded-security IP. Cadence also sells digital, custom and analog, verification and implementation EDA tools, 3D-IC and package-design capabilities, and design services. The strategic proposition is a broader set of components that can be brought together across IP, libraries, tools and services—not necessarily one bundled product. Availability, licensing and foundry support vary by product and process.
That breadth may reduce handoffs for teams already working in Cadence flows, but buyers should assess process qualification, tool compatibility, licensing, support ownership and vendor concentration. Mixed-vendor IP can add verification and timing-closure work and complicate accountability; a single-vendor relationship may simplify coordination while increasing dependence on that supplier.
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What has happened since the announcement
- April 16, 2025: Cadence announced the definitive agreement to acquire the Artisan business.
- August 26, 2025: The transaction closed, according to Arm’s filing. Cadence published its completion announcement the following day.
- October 27, 2025: Cadence said the acquired Artisan foundation IP had augmented its design-IP portfolio in its third-quarter results. Cadence’s results release also said the acquisition was expected to be immaterial to 2025 revenue and earnings.
- April 22, 2026: Cadence said its Artisan advanced-node foundation-IP portfolio was in production designs using TSMC N3 technologies as part of a collaboration with TSMC. The announcement does not name customers, report volumes or isolate revenue from Artisan IP.
Cadence reported 22% year-over-year growth in its IP business in first-quarter 2026, citing demand from AI infrastructure, high-performance computing and automotive and continued adoption of its portfolio, including foundation IP. That company-wide IP figure does not identify Artisan’s separate revenue or contribution. Cadence’s first-quarter results provide the broader context.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the acquisition means for Arm, foundries and designers
For Arm
Arm continues to develop its CPU architecture and core businesses while Artisan’s foundation-IP operation sits within Cadence. Arm reported a $131 million pretax gain on the divestiture for its fiscal year ended March 31, 2026. That is an accounting gain, not a disclosed purchase price. Arm’s financial filing reports the figure.
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For foundries and SoC designers
The acquisition puts Artisan’s process-specific IP under a supplier that also provides design tools and services. That could give customers another way to access foundry-qualified physical IP and may reduce coordination between IP and implementation teams. The benefit depends on the foundry, node, license and project; the deal does not remove the need to work with foundries, OSATs, package suppliers or other IP vendors.
For buyers, the practical questions are whether the required libraries are qualified for the chosen process, whether existing Arm or foundry rights affect access, how the IP fits the design flow, and who supports integration and updates. Foundation-IP availability alone does not resolve package yield, thermal limits, security, test coverage or system-level verification.
What is still undisclosed
Cadence and Arm did not disclose the transaction price in the cited materials. Arm’s reported $131 million pretax gain should not be treated as the deal value. Cadence also has not provided a customer-by-customer revenue breakdown or an isolated return-on-investment figure for Artisan. The TSMC N3 production-design statement is evidence of use in production designs, but not of their volume or commercial contribution.
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