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Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Repair Windows errors before they cause bigger problemsFix Now →Short answer: ASML demonstrated a 1,000-watt extreme-ultraviolet (EUV) light source in April 2025. That is a verified research and development milestone, not a commercially deployed 1,000W scanner. ASML says the technology could help push its Low-NA EUV platform toward at least 330 wafers per hour at the start of the next decade, versus about 230 wafers per hour for today’s TWINSCAN NXE:3800E. The result could expand chipmaking capacity, but only if reliability, optics, thermal management, resist performance, yield and fab bottlenecks are solved.
What ASML actually achieved
ASML says it completed its first 1,000W EUV light-source demonstration in April 2025. The company has not said that customers are already running production scanners with a commercial 1,000W source; its annual-report material describes commercialization as a future development step. The distinction matters: the demonstration validates the source technology, while a production tool must operate reliably for long periods, meet exposure specifications and pass customer qualification.
The milestone concerns the light source itself, not a claim that an entire lithography system has already doubled its throughput. ASML’s public roadmap links the source work primarily to higher productivity for its 0.33-numerical-aperture (NA) Low-NA EUV systems.
ASML previously reported a 500W prototype source in 2022. In 2018, reaching 250W was associated with volume production at approximately 125 wafers per hour, illustrating why source power is strategically important even though wattage does not translate directly into chip output.
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ASML’s 2025 annual-report strategy and stories describes the demonstration and its remaining commercial-development requirements.
Why EUV source power affects throughput
EUV lithography prints extremely small features with 13.5-nanometer light. Each wafer layer must receive a required exposure dose. More usable EUV photons arriving each second can shorten the exposure portion of the cycle, potentially raising wafers per hour and lowering lithography cost per wafer.
The practical chain is:
- Higher source power provides more EUV photons per unit time.
- The scanner may deliver the required dose in less exposure time.
- Shorter exposure cycles can raise scanner throughput.
- More scanner capacity can increase the number of wafers a fab processes without adding the same number of lithography tools.
- More completed chips follow only if yield and every other production step keep pace.
Source power is therefore a throughput input, not a yield guarantee. Defectivity, overlay, etch, deposition, inspection, packaging and test can all limit the number of sellable dies.
How ASML generates 13.5nm EUV light
Inside a near-vacuum source chamber, a generator fires microscopic droplets of molten tin with laser pulses. The laser first shapes a droplet and then drives it into plasma; that plasma emits EUV radiation. Because air absorbs EUV, the light travels through vacuum and is collected and reflected by specialized multilayer mirrors rather than ordinary lenses.
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ASML says its source repetition rate increased from approximately 60,000 to 100,000 tin-droplet plasma events per second. More events create more opportunities to generate usable light. The company also reports improved plasma recipes, laser control and methods to prevent feedback between the plasma and laser, allowing more powerful and stable pulses while improving overall power efficiency.
The optical system is exceptionally demanding. ASML says its EUV mirrors contain more than 100 precisely engineered material layers. Details such as exact pulse architecture, laser wattage and droplet speed should not be treated as confirmed specifications unless ASML publishes them.
See ASML’s explanation of EUV lenses and mirrors for the optical constraints.
What 1,000W could mean for chip production
ASML’s Q1 2026 investor-call transcript says the updated Low-NA roadmap targets at least 330 wafers per hour at the start of the next decade. That is a roadmap target, not current customer performance. ASML’s January 2026 presentation cites approximately 230 wafers per hour for the NXE:3800E, its current Low-NA production platform.
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| Milestone | Figure | What it means |
|---|---|---|
| 2018 production milestone | 250W; about 125 wafers/hour | ASML associated this source level with EUV volume production. |
| Current NXE:3800E | About 230 wafers/hour | Record throughput cited by ASML’s January 2026 presentation. |
| Low-NA roadmap | At least 330 wafers/hour | ASML target for the start of the next decade, enabled in part by source-power improvements. |
Reuters reporting, reproduced by The Business Times, said the advance could support as much as 50% greater chip-production output by 2030. That is a projected effect, not a promise that every fab or product will ship 50% more finished dies. Die size, EUV-layer count, utilization, process yield, demand and packaging capacity determine the final result.
A faster scanner can also encounter bottlenecks elsewhere. Metrology, masks, wafer handling, etch, deposition, inspection and maintenance must provide equivalent capacity. If they do not, higher EUV throughput may increase unused scanner capacity rather than finished-chip shipments.
Why a demonstration is not yet a commercial product
A source that reaches 1,000W in a controlled demonstration still has to meet production requirements over years of operation. The principal commercialization gates include:
- Lifetime and uptime: ASML must establish stable operation, maintenance intervals and mean time between failures at the higher repetition rate.
- Collector and mirror durability: More plasma events can increase debris, contamination and degradation of reflective optics.
- Thermal management: The source, collector, mirrors, vacuum hardware and scanner structure must remove additional heat without disturbing imaging stability.
- Optical transmission: Losses in the source and mirrors can reduce how much of the headline power reaches the wafer.
- Resist and mask behavior: Photon availability does not remove limits imposed by resist sensitivity, stochastic defects or mask quality.
- System integration: Wafer and reticle stages, alignment and overlay measurement must keep pace with shorter exposure cycles.
- Customer qualification: Chipmakers need guaranteed throughput, defect performance, serviceability and facility requirements before accepting a production tool.
The available announcements do not establish a commercial launch date, customer installation date, price, guaranteed uptime or cost per wafer for a 1,000W source.
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Low-NA and High-NA EUV are related but different
The 1,000W milestone should not be presented as a High-NA product announcement. Low-NA EUV systems use a 0.33 NA and form the current high-volume manufacturing platform. High-NA EUV raises NA to 0.55 to improve resolution and reduce multipatterning for future logic and memory processes.
| Platform | Numerical aperture | Primary emphasis |
|---|---|---|
| Low-NA NXE | 0.33 | Current advanced logic and memory production; ASML’s 330-wafers-per-hour roadmap is tied to this class. |
| High-NA EXE | 0.55 | Higher resolution, fewer patterning steps and future-node imaging. |
ASML lists 8nm resolution for the EXE:5200B, approximately 40% more imaging contrast than NXE systems and the ability to print features 1.7 times smaller in a single exposure. ASML’s 2025 annual report says the first full-specification EXE:5200B was delivered to a customer. Those facts describe the High-NA roadmap, not proof that the 1,000W source is already an EXE feature.
Product details are available on ASML’s EUV systems overview and the EXE:5200B product page.
The near-term roadmap for investors and industry watchers
NXE:3800E productivity now
ASML says 230 wafers per hour is immediately available to all NXE:3800E customers. Its Q1 2026 investor-call transcript also describes a productivity upgrade adding 10 wafers per hour. This is a concrete near-term improvement, separate from a future commercial 1,000W source.
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Low-NA productivity early next decade
The stated target is at least 330 wafers per hour at the start of the next decade. Reaching it will depend on source power plus stage timing, dose, optics, resist, uptime and full-system integration.
High-NA deployment
EXE tools pursue resolution and process simplification as well as productivity. ASML’s High-NA materials position the platform for future logic and memory nodes; they should not be used to infer a delivery date or throughput specification for a 1,000W Low-NA source.
What to watch next
- An ASML announcement identifying the first commercial scanner or upgrade with a 1,000W source.
- Customer installation, qualification and long-duration uptime data.
- Guaranteed throughput at a defined exposure dose, rather than source wattage alone.
- Evidence on collector lifetime, maintenance intervals and facility cooling or power requirements.
- Cost-per-wafer data and whether fab bottlenecks absorb the additional scanner capacity.
- Adoption by leading logic and memory manufacturers.
The investment and industry significance is substantial: EUV scanners are a critical bottleneck for advanced-chip capacity, and higher productivity could let fabs add output without buying a proportional number of new tools. But the financially relevant outcome is commercial, reliable wafers per hour—not the 1,000W headline by itself.
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