TSMC’s latest public statements support a real shift in semiconductor economics: newer manufacturing nodes cost more, and rising prices have largely offset rising production costs. But reports of specific increases—such as 5% to 10% across advanced nodes or changes beginning in 2027—are not confirmed as blanket TSMC policy in the company’s public materials. Even if foundry prices rise, that does not mean every chip or device will cost the same percentage more. The biggest pressure is on advanced logic and packaging; the effect on a finished product depends on yields, design choices, supplier contracts, and who absorbs the cost.
What TSMC has confirmed—and what remains reported
On its fourth-quarter 2025 earnings call, TSMC CFO Wendell Huang said each new process node carries a higher price than the one before it. He also said pricing benefits in recent years had mainly covered inflation in equipment, materials, labor, and other manufacturing costs. Pricing is only one factor in profitability, alongside utilization, productivity, capacity optimization, and the mix of technologies sold. TSMC’s Q4 2025 earnings-call transcript is the clearest public evidence for the underlying trend.
TSMC’s scale is increasingly weighted toward newer processes. In its 2025 annual report, the company said technologies it classifies as advanced—7nm and newer—accounted for 74% of wafer revenue in 2025, compared with 69% in 2024. It shipped 15.0 million 12-inch-equivalent wafers in 2025, and said N2 entered high-volume manufacturing in the fourth quarter. These figures show the growing importance of advanced manufacturing, not that every customer faced an identical price increase. TSMC’s 2025 annual report details the revenue mix and process ramp.
Industry reports have described planned increases of 5% to 10% for advanced nodes, potentially starting in 2027, as well as larger increases for particular nodes or manufacturing services. Those numbers and timing should be treated as reported claims, not confirmed company-wide policy: TSMC’s public materials cited here do not establish a universal percentage, effective date, or price applying to every customer and service. EE Times and Tom’s Hardware report on advanced-node increases; a separate Tom’s Hardware report discusses service-price increases as high as 25% in 2027. The precise figures are not verified by the cited TSMC disclosures.
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What a TSMC price increase applies to
A foundry price is not a retail price. The chain from a fab to a finished product includes several distinct costs, each of which can move differently:
| Cost or price | What it means |
|---|---|
| Wafer price | What a chip designer pays a foundry to process a wafer. It does not say how many usable chips the wafer yields. |
| Process-node price | The manufacturing price associated with a technology such as N7, N5, N3, or N2. Newer nodes generally command higher prices. |
| Packaging and testing | Costs to assemble, connect, and validate dies. Advanced services such as CoWoS, InFO, and SoIC can be especially important for complex AI and chiplet products. |
| Masks and design engineering | Up-front costs to create and qualify a design. These can weigh more heavily on smaller-volume chips because there are fewer units over which to spread them. |
| Finished chip price | The price charged by a chip company to a system maker or other customer. It reflects more than foundry charges. |
| End-device price | The price paid for a phone, graphics card, server, laptop, or other product. It also includes other components, assembly, distribution, margins, and market conditions. |
Consequently, a reported 5% to 10% increase in a foundry charge would not mechanically produce a 5% to 10% increase in a GPU, phone, or laptop price. A chip company might absorb some of it in its margin; a device maker could absorb some more; a contract might change only at renewal; or the design might be altered. The size and direction of the eventual consumer effect cannot be inferred from a wafer-price report alone.
Why leading-edge manufacturing costs more
More capital and harder process engineering
Leading-edge production requires costly lithography, inspection, metrology, cleanroom infrastructure, and process development. Each new generation also has to meet demanding targets for performance, power, reliability, and defect control. TSMC’s annual report describes continued investment in advanced processes, packaging, and manufacturing capacity. For N2, TSMC identifies a second-generation nanosheet transistor structure; its roadmap also positions A14 as a further full-node advance beyond N2. These are engineering transitions, not simple changes to a label on an otherwise unchanged factory.
Yield determines how much a wafer really produces
A wafer is not a tray of guaranteed working chips. The number of saleable dies depends on die size, defect density, process maturity, and how many defects a design can tolerate. A large chip is more likely than a small one to encounter a defect somewhere in its area, all else equal. Early production on a new process can also have different yields from a mature, well-tuned process. A higher wafer bill can therefore be offset by more good dies or more capability per die—or amplified by poor yield and large designs.
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Global capacity and packaging add to the cost stack
TSMC is expanding capacity in Taiwan and overseas. On its Q4 2025 call, management identified the ramp of more expensive overseas fabs as one factor affecting blended wafer prices. In Q1 2026, it discussed further 3nm capacity in Taiwan, Arizona, and Japan, alongside strong demand from AI, high-performance computing, smartphones, automotive, and IoT. Overseas production can improve geographic diversification, but construction, labor, operating, and supply-chain costs may differ from those in Taiwan. TSMC’s Q1 2026 call describes the capacity plans and market demand.
For AI hardware, the front-end logic wafer is only part of the bill. High-bandwidth memory, interposers, substrates, and advanced packaging can determine both cost and delivery capacity. TSMC highlights CoWoS, InFO, SoIC, and related 3D integration technologies in its 2025 technology section. A comparison that looks only at wafer pricing misses this broader system of constraints.
Why a higher wafer price is not the same as a higher transistor cost
The relevant unit is not simply dollars per wafer. A simplified way to think about cost per working transistor is:
Cost per working transistor ≈ wafer cost ÷ (good dies per wafer × transistors per die)
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This is only a simplified illustration. Real product economics also depend on yield, packaging, testing, masks, design expense, memory, substrate availability, and product-specific requirements. It nevertheless shows why wafer price alone is an incomplete measure.
Consider an illustrative example, not a TSMC measurement: suppose wafer cost rises 30%, transistor density rises 60%, and yield falls from 90% to 85%. If die size, usable design area, packaging, and other costs were held constant, the added density could more than offset the wafer-price increase in cost per transistor. But the lower yield works in the opposite direction, and a real chip may not use the extra density efficiently. If a new process raises wafer price by 50% while doubling useful transistor density and maintaining adequate yield, cost per transistor could rise much less than 50% or even fall. Conversely, a modest wafer increase can hurt badly if yields are weak or the design is very large.
The same logic applies to cost per unit of computation. A more expensive chip may still be economically worthwhile if it delivers more performance per watt, reduces the number of servers needed, or finishes a workload faster. The buyer’s comparison is often the cost of useful output, not the price of the wafer in isolation.
Why AI strengthens foundry pricing power
AI accelerators and other high-performance processors concentrate demand on advanced logic and advanced packaging. Their buyers may value availability, performance, and time to market more than the lowest possible silicon cost. Large cloud and technology companies can also monetize performance through services, so a more expensive chip may still make financial sense if it improves throughput or lowers operating costs.
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That willingness to pay is distinct from the physical cost of manufacturing. It helps explain why pricing power can be strongest in premium products even while other semiconductor markets remain cost-sensitive. TSMC’s 74% advanced-technology share of 2025 wafer revenue reflects the importance of 7nm-and-newer processes in its business; it does not mean all 2025 wafers or all semiconductor products belonged to the same market.
Who may absorb a foundry increase?
The eventual burden depends on bargaining power, contracts, competition, margins, and the value a product delivers. Possible outcomes include:
- The chip designer absorbs the cost: its gross margin falls unless it offsets the increase elsewhere.
- The designer raises its chip price: a server maker, phone company, or other customer pays more for the processor.
- The system maker absorbs it: its margin declines rather than immediately raising the device price.
- The end customer pays more: retail or enterprise pricing rises if suppliers pass enough of the cost through.
- The design changes: a company may use chiplets, move non-critical functions to a cheaper node, reduce die size, or delay a product.
- The supplier mix changes: customers may seek another manufacturing source where a technically and commercially credible alternative exists.
Large customers may have more negotiating leverage than smaller designers, but specific customer terms are not established by the public materials cited here. Nor does a rise in TSMC’s blended wafer average selling price prove that every contract became more expensive by the same amount. As management’s Q4 commentary indicates, the average can reflect several things at once: a greater share of leading-edge production, pricing, and a larger contribution from more expensive overseas capacity. Mix and contract-price changes should not be conflated.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why the impact will be uneven across electronics
The greatest direct exposure is in products that depend on advanced logic, complex packaging, or both:
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- AI accelerators and high-end GPUs.
- Server CPUs and custom high-performance processors.
- Premium smartphone application processors.
- Networking silicon and high-performance custom ASICs.
- Products that integrate advanced logic with high-bandwidth memory or sophisticated packaging.
Many microcontrollers, analog and power-management chips, sensors, connectivity parts, and automotive or industrial components use mature or specialty processes instead. They do not suddenly acquire the economics of an N2 AI processor. TSMC’s Q1 2026 commentary describes a mature-node strategy oriented toward specialty technologies and strategic segments, including automotive and industrial uses, rather than a simple shift of all production to the smallest node.
This does not make mature-node supply immune to shortages or price changes; it means the leading-edge price story is not a reliable proxy for every semiconductor category. A washing machine or car contains many kinds of chips, and their manufacturing processes, suppliers, and cost drivers differ.
Is Moore’s Law ending?
Not on the evidence of price increases alone. Moore’s Law is commonly used to describe the long-running rise in transistor density and the industry’s expectation of continued scaling; it is not a guarantee that every new chip will be cheaper, or that every generation will reduce cost per transistor by a fixed amount. New processes can still deliver more transistors, better performance, or lower power even as their development and production become more expensive.
What is under pressure is the economic assumption that more density will automatically produce cheaper useful transistors. Smaller geometries, more complex structures, high mask and design costs, yield challenges, packaging constraints, and expensive new capacity make that outcome less automatic. The defensible conclusion is that scaling remains valuable, but its benefits increasingly require a premium investment and products capable of earning a return on it—not that transistor-density improvements have stopped.
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One reported increase is not enough to establish a permanent change across the industry. The more useful signals are whether costs and prices persist across cycles and whether customers continue to find the resulting chips worth buying:
- TSMC’s future commentary on node pricing, blended wafer prices, utilization, and overseas-fab costs.
- Official customer disclosures that distinguish foundry costs from chip and system prices.
- N2 production ramp and yield progress, rather than a single media estimate for a wafer price.
- Advanced-packaging and high-bandwidth-memory availability and costs.
- Chip designers’ margins and evidence of price pass-through or design changes.
- Use of chiplets and the placement of different functions on different process nodes.
- Whether customers have credible alternatives for the particular process and product they need.
The key distinction is between a temporary rise in costs or a richer mix of premium products and a durable, broad-based change in contract pricing. TSMC’s public record already supports the narrower conclusion: leading-edge manufacturing is becoming more costly, and pricing is part of how the company manages that reality. Whether every reported increase becomes broad, persistent policy remains unconfirmed.
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