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AMD executives say Intel’s expected decision to omit simultaneous multithreading (SMT) from the future Xeon “Diamond Rapids” generation could help AMD win more server business. That is a credible competitive argument, not a confirmed market outcome: Intel has acknowledged that moving away from SMT created a disadvantage and plans to restore it, but it has not published a complete Diamond Rapids specification confirming the omission.
For enterprise buyers, the practical question is not whether SMT is “good” in the abstract. It is whether a workload gains enough throughput per licensed physical core, watt, rack unit and dollar to outweigh platform, qualification and migration costs.
What AMD executives actually said
Madhu Rangarajan’s argument
Madhu Rangarajan, AMD’s corporate vice president for compute and enterprise AI products, told CRN that AMD expects its performance advantage to widen with the next-generation EPYC “Venice” family. He linked Intel’s expected SMT omission to potential AMD share gains, arguing that SMT can deliver substantial throughput for relatively little silicon and can make per-core software licenses more productive.
Rangarajan cited performance improvements of up to 50% on some workloads. That is an AMD executive’s workload-specific claim, not a universal benchmark result: SMT does not double a core’s performance, and gains vary with contention, memory behavior, software threading and latency requirements.
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Steve Berg’s sales view
Steve Berg, AMD’s corporate vice president and general manager of the Server CPU Cloud Business Group, said AMD intends to “take advantage” of Intel’s decision. His framing focused on hyperscalers and enterprise customers, where fleet economics, qualification and utilization matter more than a single benchmark.
Both executives are interested AMD sources. Their comments explain AMD’s sales strategy; they do not independently establish that every Diamond Rapids workload will lose to EPYC.
SMT in plain English
Simultaneous multithreading lets one physical CPU core expose and execute multiple logical threads. Intel historically brands its implementation Hyper-Threading Technology; AMD generally calls the feature SMT. In a common two-way design, one core appears as two logical processors.
The second thread is not a second physical core. Both threads share execution units, caches, front-end resources and other parts of the core. A simple example is a thread waiting on memory while another thread uses execution resources that would otherwise sit idle. Throughput can rise, but two busy threads can also compete for the same scarce resource.
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AMD says its engineers estimate SMT occupies less than 5% of Zen 4 and Zen 5 core area. That is an AMD engineering estimate, not an independently verified industry-wide measurement. AMD’s technical explanation is available in its SMT overview and EPYC SMT brief.
What Intel has changed—and what remains unconfirmed
| Generation or design | SMT position | Confidence and qualification |
|---|---|---|
| Sierra Forest E-core Xeon | No SMT in the efficient-core design | Described in AMD’s technical material |
| Granite Rapids P-core Xeon | Supports SMT | Described in AMD’s account of current Xeon products |
| Diamond Rapids | Expected to omit SMT | Reported by CRN and discussed by AMD executives; Intel has not published a complete confirming specification in the available material |
| Coral Rapids | Expected to restore SMT | Roadmap detail reported by CRN; final configuration and timing require Intel confirmation |
On July 24, 2025, Intel CEO Lip-Bu Tan said the company had moved away from SMT, called that a competitive disadvantage and said Intel was reintroducing it in future products. His statement confirms the strategic reversal, not every feature of named roadmap products. See Intel’s newsroom statement.
Why SMT can affect software-license economics
Enterprise software may be licensed by physical cores, sockets, logical processors, virtual CPUs, a vendor-specific core factor or another capacity unit. If SMT raises application throughput without increasing the licensed physical-core count, an organization may get more work from the same license footprint.
- Physical-core licensing can let higher utilization improve output without adding licensed cores.
- vCPU-based cloud pricing and logical-processor licensing can produce different results.
- Some vendors apply core-factor rules that treat threads differently.
- Security, determinism or isolation policies may lead an administrator to disable SMT.
- A compute-bound workload may gain little because both threads already compete for saturated execution units.
Therefore, SMT can improve performance per licensed physical core, but it does not automatically reduce software costs. The contract and the workload’s measured utilization determine the financial effect.
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AMD’s Venice and EPYC 9006 timing
AMD announced a production ramp for Venice on May 21, 2026. In a July 23, 2026 technical article, it identified the family as EPYC 9006, based on Zen 6 and TSMC’s 2-nanometer process. AMD says configurations reach up to 256 physical cores and 512 threads per socket, with up to 16 DDR5 memory channels and PCIe 6.0. The company positions the platform for cloud, enterprise, HPC, database and AI workloads; details are in AMD’s EPYC 9006 article.
“Production ramp” is not the same as universal procurement availability. Specific SKUs, system vendors, prices, qualification status and delivery schedules should be checked before a purchase decision.
Where AMD’s market share stands
Share figures in this debate are not interchangeable:
| Measure | Reported figure | Source and limitation |
|---|---|---|
| x86 server unit shipments | 28.8% in the fourth quarter of the prior year | Mercury Research figure reported by CRN; measures units, not revenue |
| Server revenue share | 41.3% | Company-stated figure cited by CRN; revenue weights expensive processors more heavily |
| “Over 40%” server CPU share | Over 40% | AMD’s February 2026 claim; denominator, period and methodology are not shown as equivalent to the Mercury unit figure |
AMD’s February claim appears in its Google Cloud article. A shipment percentage, a revenue percentage and a company-defined market-share statement answer different questions and should not be placed in one comparison chart without their bases.
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Intel’s response and the limits of the SMT thesis
Intel fellow Srini Krishna told CRN that Xeon 6 continues to see momentum with cloud providers, telecom companies and enterprises. Intel emphasized performance, security, efficiency, platform experience and real-world deployments rather than conceding AMD’s SMT argument.
SMT is only one variable in server economics. Buyers also compare physical-core count, frequency, memory bandwidth and capacity, I/O, accelerators, power, cooling, OEM availability, cloud qualification, support, security and migration cost. Intel could offset an SMT omission with more physical cores or other platform advantages, while AMD’s SMT benefit may disappear on a bandwidth-bound or latency-sensitive application.
The competitive field is broader than AMD versus Intel. AWS, Google, Microsoft, Nvidia and others are deploying or developing Arm-based server processors, giving cloud operators another architecture to evaluate.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What enterprise buyers should measure
1. Benchmark the real workload
- Run database concurrency, web-service throughput, virtualization consolidation, analytics, HPC, inference and batch tests relevant to the fleet.
- Record throughput, tail latency, memory bandwidth, power and performance per watt.
- Test SMT enabled and disabled where the platform permits it; do not substitute thread count for measured capacity.
2. Model the license contract
- Confirm whether the vendor counts physical cores, logical CPUs, sockets, vCPUs or a core-factor unit.
- Ask whether disabling SMT changes the licensed capacity or certification status.
- Calculate cost per completed transaction or job, not just cost per processor.
3. Compare the complete platform
- Include memory channels and capacity, PCIe lanes, networking, accelerators, server power and rack density.
- Check hypervisor, operating-system and application certification.
- Verify OEM and cloud availability, warranty, support and delivery lead times.
4. Account for deployment policy
SMT may be enabled for throughput workloads and disabled for security, deterministic latency or isolation requirements. Rangarajan has also described it as a flexible deployment choice rather than an all-or-nothing policy. The setting should follow measured risk and performance requirements.
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Commercial choices beyond a headline
Current comparisons generally involve AMD EPYC 9005/Turin, Intel Xeon 6 and, when qualified, EPYC 9006/Venice. Product information is available from AMD’s EPYC page and Intel’s Xeon page. Enterprise processors are commonly sold through OEMs, distributors, cloud providers and negotiated contracts rather than one universal retail price.
Cloud testing can avoid an immediate hardware commitment through AWS EC2, Microsoft Azure Virtual Machines or Google Cloud Compute Engine. Compare region, operating system, reservation or commitment terms, storage, networking and utilization; an hourly instance price is not a standalone CPU price.
Bottom line
AMD has a plausible opening if Diamond Rapids lacks SMT while EPYC systems deliver better measured throughput, licensing efficiency or total cost for target workloads. Intel has acknowledged the strategic disadvantage and intends to restore SMT, but neither that roadmap nor AMD’s claims proves a future market-share shift. Buyers should make the decision with workload benchmarks, contract-level license math and full platform costs—not core or thread counts alone.
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