On July 2, 2002, ASM International N.V. announced that the U.S. Patent and Trademark Office had granted it three patents related to plasma-enhanced chemical vapor deposition (PECVD) of low-k dielectric films: U.S. Patent Nos. 6,352,945, 6,383,955 and 6,410,463. The announcement concerned technology for insulating copper interconnects in chips—not a finding that ASM controlled the entire low-k materials field. Its “patent high ground” phrasing was a headline metaphor, not a legal or market judgment.
What ASM announced in 2002
ASM International N.V., the semiconductor-equipment company headquartered in Bilthoven, Netherlands, said the three patents covered aspects of PECVD processes for advanced low-k dielectric films used in the back end of the line (BEOL), where a chip’s metal wiring and insulating layers are built above its transistors. ASM said the patents claimed priority to a parent Japanese application filed February 5, 1998. The company introduced its Aurora low-k materials in September 1998. ASM’s July 2002 announcement and a related release describe the grants and product positioning.
This is ASM International N.V., not the separate materials-engineering society that also uses the name ASM International.
Why low-k films mattered to chip wiring
As interconnects become denser, neighboring metal wires couple electrically. The resulting parasitic capacitance can contribute to signal delay, crosstalk and power use. A dielectric with a lower relative dielectric constant, or “k,” reduces capacitance between those wires compared with a higher-k insulator such as conventional silicon dioxide.
Quick wins for a faster PC:
Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →#1 Best Overall
- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
Low-k dielectrics therefore target interconnect performance; they do not directly make the transistors switch faster. Their practical value depends on whether the film can also withstand the fabrication and use conditions of a copper wiring stack.
What Aurora and Eagle referred to
Aurora was ASM’s family of low-k films, described as organosilicate glass (OSG), also called carbon-doped oxide (CDO). Eagle was the company’s PECVD equipment platform for depositing those films. The patents were associated with related elements of film formation, including material characteristics, organic silicon precursors and plasma-deposition methods; that high-level description should not be mistaken for a complete summary of each patent’s claims.
Rank #2
- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
For U.S. Patent No. 6,410,463, a third-party patent summary describes a plasma-reaction method for forming a low-dielectric-constant film on a semiconductor substrate and identifies a reaction-gas residence time of at least 100 milliseconds. That detail is specific to the summary of this patent and does not establish the scope of the other two grants. Patent 6,410,463 summary.
What performance ASM claimed—and what the numbers mean
ASM described Aurora as having a dielectric constant below 3.0 and said it could be deposited on 200 mm and 300 mm wafers. The company also promoted deposition on a hot wafer without a separate anneal step, thermal stability and mechanical strength compared with other low-k films, and compatibility with multilayer copper interconnects. These are company-reported product claims, not independent comparative measurements in the cited announcement. EE Times’ July 2, 2002 coverage.
Rank #3
- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
ASM also said it saw a path to films below k = 2.4 for 65 nm and smaller technology nodes. That was a stated future target, not evidence that the 2002 product already delivered that value. The company positioned Aurora for approximately 130 nm to 90 nm process generations and said several chipmakers were working with the technology, with chip shipments expected in 2002. The report does not identify those customers or confirm which products entered production.
Why a low dielectric constant was not enough
Reducing k can conflict with mechanical robustness. More porosity or carbon modification can help lower a film’s dielectric constant, while potentially making it more vulnerable to cracking, delamination, moisture, plasma damage or deformation during chemical-mechanical planarization. A usable interconnect dielectric must survive deposition, patterning, cleaning, subsequent thermal steps, packaging and thermal cycling, while adhering to copper, barrier and neighboring dielectric layers.
Rank #4
- Method: CZ ; Size: 4inch ;
- Type: P-Type ; Dopant: B ; Orientation: 100 ;
- Resistivity:1-10Ω ; Thickness: 525um±25 ;
- Front Side: Polished ; Back Side: Etched ; TTV<10um;
- [Nanosource] High Quality Silicon Wafer. Customized Products Available.
That is why ASM’s emphasis on mechanical strength and thermal stability mattered as a process-integration argument. But the 2002 sources do not provide independent comparative data for strength, adhesion, moisture resistance, yield or reliability. Nor do they establish a quantified cost saving. Avoiding a separate anneal could simplify a process flow, as ASM suggested; no cost-per-wafer, throughput, energy, yield or ownership-cost figures were supplied.
What the three patents do—and do not—establish
A patent grant gives its owner rights defined by the claims in that particular patent. It does not by itself establish ownership of every material with a similar dielectric constant, every PECVD reactor or every carbon-doped oxide process. A competing process could produce a similar film while using different materials or conditions; whether that process infringes would depend on the patent claims and facts, not on the shared label “low-k.”
Best Value
- Genuine Silicon Wafer: crafted from high-purity silicon, this 12 inch silicon wafer features a precision double-side polished surface, delivering exceptional smoothness and mirror-like reflectivity on both sides, fitting well with tech decor needs; Please note: wafer pattern may vary from the product images
- Genuine Uncut Ic Silicon Wafer: this is a genuine uncut IC silicon wafer, not a replica or model; It preserves the original circular wafer form applied in semiconductor manufacturing, allowing you to experience real chip substrate material up close
- 12 Inch Large Size Versatile Display: with a full 12 inch diameter, this wafer provides a striking visual presence compared to smaller 6 or 8 inch wafers; Its larger size enhances the natural light interference patterns, creating subtle rainbow reflections under different lighting, ideal for desk display, office decor, exhibitions, or as a centerpiece for tech-inspired spaces; Silicon crystals are very fragile, please handle them as gently as possible
- Practical Stem Education Tool: a valuable teaching tool for STEM education, this semiconductor substrate helps illustrate how integrated circuits are manufactured; Great for classrooms, labs, or personal learning, it allows students to better understand wafer structure, fabrication processes, and the foundation of modern electronics in a tangible way
- Tech-inspired Gift: combining science and art, this silicon wafer makes a unique gift for engineers, programmers, students, and tech lovers, suitable for various gifting occasions without being overly decorative
The 2002 announcement establishes that ASM reported three grants in a related technical area. The available sources do not provide enough claim-by-claim analysis to determine the full scope of each patent, how the claims relate to one another, whether they faced validity challenges, or their current legal status. They also do not establish infringement suits, licensing control, market-share leadership or exclusive ownership of low-k technology. Patent ownership, enforceability, freedom to operate and commercial adoption are separate questions.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How Aurora developed after the announcement
In 2004, ASM announced an enabling process for ultra-low-k materials involving plasma-deposited benzocyclobutene (BCB), a development distinct from simply extending the 2002 Aurora patent announcement. ASM’s 2004 announcement.
In 2006, ASM and IMEC reported three generations of Aurora low-k and silicon-carbide barrier materials, with Aurora k-values around 3.0 to 2.3 and work aimed at 45 nm-or-smaller feature sizes. This shows continued materials development and collaboration; it does not demonstrate that Aurora became an industry standard or held a dominant market position. ASM and IMEC’s 2006 announcement.
Low-k PECVD remained a competitive area rather than a field defined by one 2002 patent announcement. Later coverage describes Applied Materials promoting its own low-k PECVD materials for advanced copper wiring. That later context does not resolve the scope or legal effect of ASM’s patents. Later coverage of Applied Materials’ chip-wiring technology.
Recommended Free Tools
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.




