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Ambiq’s HeliosRT and HeliosAOT address the same embedded-AI problem in different ways: HeliosRT interprets models using a TensorFlow Lite for Microcontrollers–derived runtime, while HeliosAOT compiles models into C code for firmware. Ambiq described performance and memory gains for both, but the figures in the August 2025 coverage are company claims, not independent benchmark results. Separately, Ambiq completed its IPO in July 2025, raising $110.4 million in gross proceeds before expenses.
What Ambiq announced
An Embedded article published August 1, 2025 covered two software approaches for running AI models on constrained embedded hardware, including Ambiq’s Apollo family: HeliosRT and HeliosAOT. The distinction is architectural. HeliosRT retains interpreter-style execution; HeliosAOT converts a model ahead of time into C code that can be built into firmware.
The same article reported that Ambiq had gone public. These are separate developments: the runtime announcement concerns deploying inference on embedded devices, while the IPO concerns how the company raised capital.
How HeliosRT and HeliosAOT differ
| Approach | How inference runs | Workflow and trade-off |
|---|---|---|
| HeliosRT | Interpreter-style model execution; described as a fork of TensorFlow Lite for Microcontrollers (TFLM). | Intended to retain a familiar TensorFlow/TFLM model workflow while using kernels optimized for Ambiq hardware. Interpretation remains part of runtime execution. |
| HeliosAOT | The model is compiled ahead of time into C code and incorporated into firmware. | Operators and metadata can be resolved at compile time, and only required kernels included. This avoids interpreter scheduling and lookup work during inference, but requires a model-compilation and firmware-integration workflow. |
The choice is not simply “which is faster?” Interpreter deployment may suit a team that wants to stay close to an established TFLM workflow. Ahead-of-time compilation may be attractive when reducing runtime overhead or planning memory placement matters. Actual results depend on the Apollo device, model, supported operators, conversion path, and how the firmware uses memory.
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What Ambiq claimed about speed and memory
Embedded attributed the following figures to Ambiq; the article did not present an independent, controlled side-by-side benchmark matrix:
- 10–30% better model performance: Ambiq said specialized lookup-table optimizations could produce this improvement.
- 15–50% lower memory footprint: Ambiq reported this range for ahead-of-time compiled models compared with interpreter-based deployment.
- Almost 5× better performance: Ambiq vice president of AI Carlos Morales said a HeartKit example achieved this after changing only the runtime, without modifying the model.
Those figures should be treated as vendor-reported results, not a guarantee for a different model, chip, or application. The article does not specify a common test setup that would let readers compare the two runtimes independently. Morales described the work as a set of optimized kernels for operations common in edge-AI models; the reported HeartKit result is an example, not evidence that every model will see the same gain.
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Memory planning in HeliosAOT
The article describes HeliosAOT as supporting scratch-buffer reuse and configurable allocation across TCM, SRAM, and MRAM. Developers can use a YAML file to specify where layers should go. Ambiq principal AI engineer Dr. Adam Page said the generated code mirrors the network structure, which he described as making it easier to follow.
These are implementation options described for the approach, not a claim that every Apollo device has all three memory types or identical capacities and performance. Whether placement helps depends on the target hardware and the model’s memory demands. Developers evaluating it should examine peak RAM, firmware size, layer placement, and the memory available on their specific device.
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How to evaluate the runtimes for a project
Because the published figures do not establish a universal winner, compare both approaches on the actual target and model. A useful evaluation should include:
- Operator coverage: Confirm that the required model operations are supported in the intended runtime and conversion workflow.
- End-to-end latency: Measure inference on the target Apollo device with the application’s real model and settings.
- Peak RAM and firmware footprint: Track temporary scratch memory as well as the code and data added to the firmware.
- Integration effort: Account for preserving an interpreter-based model workflow versus compiling and integrating generated C code.
- Memory placement: Verify which memory regions the selected device exposes and whether assigning layers or buffers to them meets the application’s requirements.
Ambiq’s September 23, 2025 neuralSPOT SDK V1.2.0 announcement later described HeliaRT beta integration for Apollo510 and Apollo510B, and HeliaAOT integration as experimental. Those later names and status descriptions provide dated product context; they do not establish the current, October 2026 release status, licensing, supported-chip matrix, or performance of HeliosRT and HeliosAOT.
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What “goes public” means in Ambiq’s case
Ambiq Micro’s IPO was a 2025 financing event, not a software-release milestone. The company’s July 31, 2025 closing announcement says it sold 4.6 million shares at $24 per share, for $110.4 million in gross proceeds before expenses. Ambiq shares began trading on the New York Stock Exchange on July 30, 2025, under the ticker AMBQ.
The $110.4 million is the definitive close figure cited in the company’s announcement. It differs from the $96 million in expected gross proceeds reported at IPO pricing: the offering was upsized and the underwriters exercised their option. A company annual report filed with the SEC also identifies the July 31, 2025 IPO close and the AMBQ ticker. Neither historical offering figures nor the ticker establishes the stock’s price or investment outlook today.
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The announcement shows Ambiq presenting an interpreter-based option and a compiled-code option for embedded inference, alongside memory-planning features and vendor-reported performance figures. It does not establish that either runtime is faster or smaller for every workload, nor does it provide enough independent test data to settle that question. For developers, the useful comparison is a measurement on the intended chip and model. For readers following the company as an investment, the IPO details are historical transaction facts, not a current valuation or recommendation.
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