TSMC announced volume production of its 40nm logic processes on November 17, 2008. The announcement covered two versions: 40G, aimed at performance-focused chips, and 40LP, designed for lower-power products. TSMC said customer product qualification was complete and first customer wafers had entered production in October.
When did TSMC move 40nm to mass production?
The milestone was announced on November 17, 2008. TSMC called it “volume production,” rather than mass production, and said both 40nm General Purpose (40G) and Low Power (40LP) had passed process qualification and reached first wafers out on schedule. First customer wafers entered production after product qualification was completed in October. TSMC’s announcement and its qualification announcement distinguish the October production activity from the later public volume-production announcement.
What did TSMC’s 40nm process target?
TSMC positioned 40nm as a way for chip designers to trade among performance, leakage, active power and density, with design support intended to help customers implement products on the node. These were TSMC’s published process claims in 2008, not guarantees for every design or finished chip.
40G: performance-oriented designs
40G targeted CPUs, GPUs, game consoles, networking equipment, FPGAs, hard-disc-drive devices and related products. TSMC said that, compared with its 65nm general-purpose process, 40G could deliver up to 30% more speed at the same leakage, or up to 70% lower leakage at the same speed. It also cited up to 45% lower active power. These are alternative “up to” comparisons, not outcomes that can all be assumed simultaneously.
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40LP: lower-power designs
40LP was aimed at cellular baseband chips, application processors, portable consumer devices and wireless connectivity. TSMC said it could reduce leakage by up to 46% and active power by up to 50% versus its 65LP process at the same speed. The comparison is specifically against 65LP, rather than 40G or every 65nm design.
Density and power claims
At the March 24, 2008 unveiling, TSMC described up to 2.35 times the raw gate density of 65nm and up to 15% active-power down-scaling versus 45nm. TSMC also reported a 0.242 µm² SRAM cell size. The density figure is a raw gate-density comparison; it does not mean a complete chip necessarily shrinks by the same ratio, since memory, wiring and design choices affect total die area. The unveiling release provides those initial targets.
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40G versus 40LP
| Attribute | 40G | 40LP |
|---|---|---|
| Primary target | Performance-focused logic, including CPUs, GPUs, consoles, networking, FPGAs and storage devices | Low-power logic, including cellular baseband, application processors, portable devices and wireless connectivity |
| Published trade-off | Up to 30% faster at the same leakage, or up to 70% lower leakage at the same speed, versus TSMC 65nm GP; up to 45% lower active power | Up to 46% lower leakage and up to 50% lower active power at the same speed versus TSMC 65LP |
| SRAM cell size | TSMC published 0.242 µm² for the 40nm platform; the release does not assign a distinct figure to each version | TSMC published 0.242 µm² for the 40nm platform; the release does not assign a distinct figure to each version |
| Design enablement | Libraries, IP, design flow, engineering service and monthly CyberShuttle multi-project-wafer prototyping were part of TSMC’s 40nm ecosystem | The same platform ecosystem was described for the 40nm offering |
TSMC’s November announcement describes the two variants and their target applications; the figures above are company-reported maximums from 2008. See the release.
How the 40nm rollout unfolded
- March 24, 2008: TSMC unveiled 40G and 40LP and expected first wafers out in the second quarter. The unveiling announcement records the plan and initial technical targets.
- October 2008: Product qualification was completed and first customer wafers entered production, according to TSMC’s qualification announcement.
- November 17, 2008: TSMC announced volume production of both 40nm variants.
- Later corporate history: TSMC’s technology timeline records 40nm volume production for multiple customers in 2008. TSMC’s logic technology history places the node in the company’s broader process timeline.
What changed technically—and what the milestone meant
TSMC’s technology history identifies 193nm immersion lithography as part of its 40nm process. Contemporary coverage also described ultra-low-k material and a low-power triple-gate-oxide option, but those implementation details do not change the basic distinction between 40G and 40LP: designers chose a process variant suited to the product’s performance and power priorities. EE Times’ contemporary coverage discusses those technical elements.
For a foundry customer, volume production is more than a node announcement: it indicates the process has moved beyond development and qualification into manufacturing for customer designs. TSMC also emphasized an accompanying design ecosystem—libraries, intellectual property, design flow, engineering support and monthly CyberShuttle multi-project wafer prototyping—so customers could develop and test designs using shared wafer capacity.
The launch was significant to TSMC’s business as a manufacturing capability, not as the release of one named consumer product. The company said 65nm and smaller processes accounted for 27% of its wafer revenue in the fourth quarter of 2008, showing that advanced nodes were already a meaningful part of its manufacturing mix. That figure is a share of TSMC wafer revenue for that quarter, not a measure of 40nm revenue alone. TSMC’s fourth-quarter 2008 results report the revenue mix.
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