Silvaco Group and Fraunhofer ISIT announced an R&D collaboration on June 24, 2025, to develop next-generation gallium-nitride (GaN) devices using Silvaco’s design and simulation tools alongside ISIT’s 8-inch post-CMOS prototyping environment. The announcement connects the work to Europe’s APECS pilot line under the EU Chips Act, but it describes a research partnership—not a production contract or a report of completed device results.
What the two organizations announced
The collaboration is intended to accelerate development of next-generation GaN power devices. Fraunhofer ISIT will use Silvaco’s Power Devices Solution and design-technology co-optimization (DTCO) flow to explore device concepts and process modules. The stated scope also includes power and sensor devices, with ISIT’s environment supporting emerging GaN and MEMS technologies.
Silvaco provides electronic-design-automation software; Fraunhofer ISIT contributes applied semiconductor and microsystems development and fabrication capabilities. ISIT says its work with industrial partners is a route toward commercialization, but the announcement does not say that this particular collaboration has resulted in a commercial product.
How the DTCO workflow is intended to help
DTCO brings device design and process development into an iterative workflow. Rather than treating a device concept and the process needed to make it as separate tasks, teams can evaluate how design choices and process modules affect one another. The stated aim here is to accelerate prototyping and evaluation of new process modules and device concepts in ISIT’s post-CMOS environment.
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The announced workflow names four Silvaco tools: Victory TCAD, Utmost IV, SmartSpice and Victory Design of Experiments (DOE). The releases identify them as components of the DTCO flow, but do not assign a specific task to each application or publish a detailed process recipe. Victory DOE is named in connection with design-of-experiments work; beyond that, claims about exactly how each tool is configured in this collaboration would go beyond what the announcements establish.
- Victory TCAD: part of the named toolset for the device-development flow.
- Utmost IV: included in the tools ISIT will use for DTCO.
- SmartSpice: included in the same announced flow.
- Victory DOE: included for design-of-experiments work intended to support evaluation of design and process options.
In practical terms, the partnership combines simulation and design tools with access to an applied-fabrication setting. That can support investigation of concepts before decisions about further development or commercialization. The public releases do not quantify any resulting reduction in development time or establish measured performance improvements.
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Why the 8-inch post-CMOS environment matters
ISIT describes its site as a major German location for 8-inch post-CMOS processing, including MEMS and GaN-on-X technologies. The partnership’s prototyping context is therefore an 8-inch wafer environment capable of exploring GaN and MEMS processes—not a disclosed high-volume production line for a named device.
That setting gives the collaboration a way to evaluate process modules and device concepts in an applied fabrication environment. The releases do not provide wafer yields, production volumes, a manufacturing schedule, or a commitment to move any particular concept into commercial production.
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How APECS and the EU Chips Act fit in
Fraunhofer ISIT’s announcement connects the collaboration to its participation in APECS, a pilot line under the EU Chips Act. APECS’s news listing recorded the collaboration on June 30, 2025, six days after the June 24 announcement by Silvaco and ISIT.
This establishes a European semiconductor-policy context for the work: an applied research institute participating in a pilot line is collaborating with a commercial EDA provider on GaN and related device development. It does not, by itself, establish that the alliance received a particular amount of EU funding, that APECS directly finances this specific work, or that the partners have made a production commitment.
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What the announcement establishes—and what remains unknown
| Topic | What is established | What the releases do not state |
|---|---|---|
| Parties and date | Silvaco Group and Fraunhofer ISIT announced an R&D collaboration on June 24, 2025. | A contract term or a schedule of milestones. |
| Technical focus | Next-generation GaN power devices, with related power, sensor and MEMS work. | Completed device results or quantified performance targets. |
| Tools and workflow | Victory TCAD, Utmost IV, SmartSpice and Victory DOE are named in the DTCO flow. | A detailed division of tasks among the tools or the specific process recipe. |
| Fabrication context | Prototyping and process exploration in ISIT’s 8-inch post-CMOS environment. | Yield, production volume, or a commitment to manufacture a product at scale. |
| Commercial and financial terms | ISIT describes industrial partnerships as a path toward commercialization. | Collaboration budget, contract value, IP ownership, or commercial terms. |
| European policy context | ISIT links the work to its APECS participation under the EU Chips Act; APECS listed the collaboration on June 30, 2025. | A specific funding award for this collaboration. |
Silvaco’s Eric Guichard, senior vice president and general manager of its TCAD Division, said the collaboration was “a significant step forward in strengthening Europe’s semiconductor capabilities and driving the global evolution of GaN devices.” That is the company’s characterization of the partnership, not a report of measured technical or commercial outcomes.
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