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Tenstorrent’s Asia momentum is centered on Japan: it is contributing RISC-V, chiplet and AI-accelerator technology to an edge-computing development effort linked to Rapidus’s planned 2nm manufacturing process. Japan’s Leading-edge Semiconductor Technology Center (LSTC) selected Tenstorrent IP for an edge-AI accelerator in February 2024, and Tenstorrent said it would collaborate with Rapidus on the project. The announcements show a development roadmap—not a commercially shipping Tenstorrent chip made at Rapidus.
What is the Tenstorrent–Rapidus partnership?
It is a joint effort to develop semiconductor intellectual property (IP) for AI edge devices using a planned 2nm logic process. Tenstorrent brings RISC-V CPU technology, chiplet design and AI-accelerator architectures. Rapidus’s intended role is advanced-logic process development and manufacturing, together with packaging capabilities. The companies announced the IP-development partnership in November 2023; Tenstorrent announced in February 2024 that LSTC had selected its RISC-V and chiplet IP for an edge 2nm AI accelerator and that it would work with Rapidus on the project.
This is not an announcement of a finished chip, a retail device or a confirmed production order. It describes design and process-development work intended to bring Tenstorrent technology into a Japanese semiconductor ecosystem.
Why focus on edge AI?
Edge computing puts processing closer to where data is generated—such as in a robot or other device—rather than relying exclusively on a remote data center. Japan’s METI material describes the Rapidus–Tenstorrent effort as an integrated semiconductor-and-software project aimed at edge applications including robotics. That makes the project’s stated target distinct from a claim that it is building a conventional hyperscale data-center accelerator.
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For Tenstorrent, the partnership offers a route to develop its IP for a new process and application setting. For Rapidus, working with an IP company connects its foundry ambitions with a prospective design and use case. Neither point, by itself, establishes that a production-ready product or customer deployment exists.
How the Japan effort has progressed
| Date | Milestone | What it establishes |
|---|---|---|
| Nov. 16–17, 2023 | Tenstorrent and Rapidus announced a joint IP-development partnership for AI edge devices based on 2nm logic. Tenstorrent announced the agreement Nov. 16; Rapidus issued its announcement Nov. 17. | A planned collaboration between Tenstorrent’s AI-computing design work and Rapidus’s advanced-logic development and manufacturing ambitions. |
| Feb. 27, 2024 | Tenstorrent said LSTC selected its RISC-V and chiplet IP for an edge 2nm AI accelerator and that it would collaborate with Rapidus. | A named Japanese project and selection of Tenstorrent IP; not evidence of a completed or shipping accelerator. |
| 2024–2025 | Tenstorrent’s newsroom records a Japan engineering-training project commissioned by NEDO, alongside continued work with Rapidus. | Additional Japan-facing activity beyond the initial partnership announcement. |
| June–July 2025 | Rapidus reported that more than 200 advanced tools had been connected at its IIM-1 facility by June 2025. In a July 2025 announcement, it also reported prototyping 2nm gate-all-around (GAA) transistors and said its process design kit (PDK) was intended for advance customers in Q1 2026. | Reported facility and process-development milestones, plus a stated future PDK target. These do not demonstrate volume production of a Tenstorrent-designed chip. |
These milestones are reported by Tenstorrent, Rapidus and Japan’s METI. The Q1 2026 PDK date was a target in Rapidus’s July 2025 announcement; the available announcements do not establish whether that release subsequently occurred.
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When will Rapidus make 2nm chips at scale?
Rapidus originally said IIM-1 would start pilot-line operations in April 2025 and targeted mass production in 2027. Those are roadmap dates, not proof that either milestone was achieved. Its later updates cited more than 200 connected tools and prototype 2nm GAA transistors, but the announcements cited here do not give a Tenstorrent chip’s production date, manufacturing yield or commercial shipment schedule.
The distinction matters: transistor prototypes and a facility being equipped are meaningful steps in process development, but they are not the same as qualifying a process for a customer design and making that design in commercial volume. No partnership revenue figure or performance benchmark is established in the cited announcements.
What does “momentum in Asia” mean here?
Tenstorrent Chief Customer Officer David Bennett said the company had “tremendous momentum with our customers in the Asia Pacific region” and was proud to discuss its Japan work. That is the company’s own characterization. The concrete Japan activity behind it includes the LSTC IP selection, the Rapidus collaboration and the NEDO-commissioned engineering-training project recorded in Tenstorrent’s newsroom.
The evidence therefore supports a stronger Japanese development presence and an active roadmap. It does not establish broader regional sales growth, a customer shipment, or commercial success for a Rapidus-made accelerator.
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Can you buy a Tenstorrent–Rapidus accelerator?
The available announcements do not establish that a Tenstorrent-designed 2nm accelerator made by Rapidus is for sale. Tenstorrent’s newsroom records the launch of Wormhole-based developer kits and workstations in July 2024, but those are separate developer products; the announcement does not make them Rapidus 2nm chips. Current stock, retail availability, geography and any Amazon listing have not been verified here.
For a buyer, the practical distinction is between existing developer hardware and a future chip-development program. A Wormhole kit should not be treated as a way to buy or evaluate the announced Rapidus 2nm design.
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