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NVIDIA’s Vera Rubin Superchip is a data-center compute subsystem—not a consumer graphics card—with one 88-core Vera CPU, two Rubin GPUs and eight visible SOCAMM2 memory modules on a single highly integrated board. NVIDIA first showed the hardware publicly at its GTC 2025 keynote on October 28, 2025. By August 2026, the reveal had become part of NVIDIA’s production roadmap: Rubin-based products were expected from partners during the second half of 2026, rather than being ordinary retail components available to buy today.
The board’s importance is its integration. It combines CPU memory, GPU HBM4 and high-bandwidth NVLink-C2C connectivity in a compact server subsystem designed for AI training, inference, reinforcement learning, scientific computing and agentic-AI workloads.
What NVIDIA actually revealed
The hardware shown in October 2025 was a board-level Vera Rubin Superchip. It was not a single monolithic silicon die and not a standalone workstation motherboard. “Superchip” describes an integrated compute configuration containing separate CPU and GPU packages that are designed to operate together inside a larger server or rack-scale system.
Tom’s Hardware’s examination of NVIDIA’s presentation showed three principal compute packages: one Vera CPU positioned between two Rubin GPU packages. Eight SOCAMM2 modules surround the CPU area. The board also includes large GPU heatspreaders, two upper NVLink backplane connectors and bottom-edge connections for power, PCIe, CXL and related system interfaces.
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- NVIDIA Volta GV100 Architecture — 4,608 CUDA Cores, 640 1st-Gen Tensor Cores delivering 14 TFLOPS FP32 and 112 TFLOPS deep learning performance for AI training, inference, HPC, and scientific computing workloads
- 32GB HBM2 ECC Memory — 900 GB/s Bandwidth — High-bandwidth memory on a 4096-bit bus with ECC error correction provides the memory capacity and throughput required for the largest AI models, simulations, and datasets
- PCIe 3.0 x16 Interface — 250W TDP — Standard PCIe Gen3 connectivity with passive cooling designed for enterprise rack server deployment in HPE ProLiant, Dell PowerEdge, and Supermicro platforms with adequate chassis airflow
- NVLink — Scale to 96GB Unified Memory — Connect two V100 GPUs via NVLink at 300 GB/s bi-directional bandwidth to scale GPU memory from 32GB to 96GB for larger AI training and HPC workloads
- Multi-Precision Computing — Supports FP64 (7 TFLOPS), FP32 (14 TFLOPS), FP16 (112 TFLOPS) and INT8 precision modes for flexible deployment across training, inference, and scientific simulation workloads
Unlike a conventional PC motherboard, it does not present a familiar collection of cabled connector slots. Its connectors are intended to link the board into specialized server infrastructure, including cooling, power delivery, networking and other rack-level components.
Tom’s Hardware’s original report provides the key visual evidence for the board layout and the eight visible SOCAMM2 modules.
Vera Rubin Superchip specifications
| Specification | Vera Rubin Superchip |
|---|---|
| Compute configuration | 1 Vera CPU plus 2 Rubin GPUs |
| CPU cores | 88 custom Olympus cores |
| CPU memory | 1.5 TB LPDDR5X |
| CPU memory bandwidth | Up to 1.2 TB/s |
| GPU memory | 576 GB HBM4 total, or 288 GB per GPU |
| GPU HBM4 bandwidth | Up to 44 TB/s across both GPUs |
| NVLink-C2C | Up to 1.8 TB/s |
| NVLink GPU bandwidth | 7.2 TB/s |
| NVFP4 inference | 100 PFLOPS |
| NVFP4 training | 70 PFLOPS |
| FP8/FP6 training | 35 PFLOPS |
| INT8 | 500 TOPS |
| FP16/BF16 | 8 PFLOPS |
| FP32 | 260 TFLOPS |
| FP64 | 67 TFLOPS |
These are NVIDIA’s published platform specifications, not independent benchmark results. The PFLOPS figures are precision-specific: 100 PFLOPS refers to NVFP4 inference, while 70 PFLOPS refers to NVFP4 training. Those numbers should not be compared directly with FP32 or FP64 results, because lower-precision formats are used for different AI workloads and calculations.
What the 88-core Vera CPU contributes
Vera is NVIDIA’s custom Arm-compatible data-center CPU, built around 88 custom Olympus cores. NVIDIA positions it for workloads surrounding AI acceleration, including agent orchestration, reinforcement-learning environments, data processing, analytics, runtime and compiler tasks, and tool or sandbox execution.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesThe CPU supports Armv9.2 compatibility, Spatial Multithreading and a second-generation Scalable Coherency Fabric, according to NVIDIA’s Vera announcement. Its CPU-side memory is LPDDR5X delivered through SOCAMM modules, with NVIDIA listing up to 1.5 TB of capacity and up to 1.2 TB/s of bandwidth.
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NVIDIA’s CPU performance and efficiency claims are workload-specific and vendor-supplied. They should not be read as proof that Vera is universally faster than every competing AMD or Intel server CPU.
What the two Rubin GPUs provide
The Rubin GPUs are the accelerator portion of the Superchip. Each GPU has 288 GB of HBM4 memory, giving the two-GPU configuration 576 GB in total. Each GPU is listed with up to 22 TB/s of HBM4 bandwidth, or 44 TB/s across the pair.
The GPUs also provide the headline AI compute figures:
- 50 PFLOPS of NVFP4 inference per GPU, or 100 PFLOPS for the Superchip.
- 35 PFLOPS of NVFP4 training per GPU, or 70 PFLOPS for the Superchip.
- 3.6 TB/s of sixth-generation NVLink bandwidth per GPU.
The 576 GB of HBM4 is not the same memory as the 1.5 TB of CPU-side LPDDR5X. HBM4 is attached to and optimized for the Rubin GPUs, while LPDDR5X in SOCAMM modules serves the Vera CPU. They form different levels of the system’s memory hierarchy rather than one undifferentiated pool.
What the eight SOCAMM modules mean
SOCAMM is NVIDIA’s compact memory-module format for dense AI-server designs. The eight visible SOCAMM2 modules shown on the board use LPDDR memory and belong to the Vera CPU’s memory subsystem.
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- Memory Size: 16 GB GDDR6 ECC.
- Memory Bus Width: 128-bit.
- Memory Bandwidth: 200 GB/s.
- CUDA Cores: 1280.
- Peak Single Precision floating point performance: 18 Tflops (GPU Boost Clocks).
It is important not to assume that eight visible modules automatically means eight independent memory channels or that each module has a fixed capacity. Module count, channel arrangement and final capacity depend on the production design. NVIDIA publishes up to 1.5 TB of LPDDR5X CPU memory for the Superchip, while the physical reveal showed eight modules; the two facts should be reported separately rather than used to infer an exact per-module configuration.
In short: the SOCAMMs are compact CPU memory. They are not HBM stacks for the Rubin GPUs.
Why NVLink-C2C matters
Vera and the Rubin GPUs communicate through NVLink-C2C rather than relying only on conventional PCIe connections. NVIDIA lists up to 1.8 TB/s of coherent CPU-GPU bandwidth for the Superchip.
That matters when CPU-controlled orchestration, data preparation or reinforcement-learning activity must exchange information rapidly with GPU workloads. A faster coherent connection can reduce data-movement bottlenecks compared with a PCIe-centric design.
The trade-off is tighter platform coupling. A Superchip depends on NVIDIA’s interconnects, firmware, cooling, power delivery and software ecosystem. It is therefore less like a modular server that can be upgraded with commodity components and more like a validated infrastructure building block.
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Superchip versus the NVL72 rack
The board-level Superchip should not be confused with NVIDIA’s larger Vera Rubin NVL72 system.
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Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →| Product level | Configuration | Purpose |
|---|---|---|
| Vera Rubin Superchip | 1 Vera CPU and 2 Rubin GPUs | Integrated compute subsystem |
| Vera Rubin NVL72 | 36 Vera CPUs and 72 Rubin GPUs | Rack-scale AI system |
| HGX Rubin NVL8 | 8 Rubin GPUs | Rubin platform for x86-based generative-AI systems |
NVIDIA’s broader Vera Rubin architecture also includes networking, storage, DPUs, switches and other rack- and pod-scale infrastructure. The Superchip is one building block within that hierarchy, not the entire supercomputer.
The HGX Rubin NVL8 route is especially relevant for organizations that want Rubin GPUs while retaining an x86-based host architecture. That makes it a different choice from the more tightly coupled Vera CPU design.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Who is it for?
The Superchip is aimed at large AI labs, hyperscalers, cloud providers, HPC installations and enterprises procuring validated data-center systems. Its strengths are high CPU-GPU communication bandwidth, substantial CPU memory capacity, large GPU HBM4 pools and dense scaling into NVLink-based systems.
Likely workloads include agentic inference, model training, reinforcement learning, scientific computing and high-concurrency AI services. It is not a sensible target for a home PC, gaming system, ordinary workstation or self-built PCIe server.
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Availability and buying reality
NVIDIA’s original 2025 reveal pointed toward production around late 2026. Subsequent NVIDIA announcements in 2026 said Rubin had reached full production and that Rubin-based products were expected from partners during the second half of 2026. NVIDIA also said OEM and supply-chain partners were manufacturing Vera Rubin systems at scale.
That does not mean the pictured board is a normal retail product. The practical buying routes are qualified OEM servers, cloud instances or large infrastructure agreements. NVIDIA’s public materials reviewed for this article do not list a standalone price for the Superchip.
NVIDIA has identified AWS, Google Cloud, Microsoft Azure, Oracle Cloud Infrastructure and cloud partners including CoreWeave, Lambda, Nebius and Nscale as expected or early deployment channels. Exact pricing will vary by provider, region and contract structure.
Server manufacturers named by NVIDIA include Dell Technologies, HPE, Lenovo and Supermicro. Final OEM systems may differ from the revealed board in enclosure, cooling, power configuration and other implementation details.
What remains unknown
- A public standalone retail price for the Superchip board.
- Whether every production implementation will use the exact visible board layout.
- OEM-specific configurations, clocks, power envelopes and cooling designs where NVIDIA has not published complete details.
- Independent benchmarks covering real-world training, inference, HPC and total cost of ownership.
- Customer-facing availability by region and cloud provider.
NVIDIA has promoted comparative claims such as lower inference cost, higher agent throughput and fewer GPUs for particular workloads. Those statements should be treated as NVIDIA claims tied to their stated baselines, models and precision—not as universal independent performance conclusions.
Bottom line
The Vera Rubin Superchip’s significance is not simply that it has an 88-core CPU. It is a tightly integrated CPU-plus-GPU subsystem: one Vera CPU with large LPDDR5X memory, two Rubin accelerators with 576 GB of HBM4, eight visible SOCAMM2 modules and up to 1.8 TB/s of NVLink-C2C bandwidth.
For infrastructure buyers, the key decision is architectural. The Superchip favors organizations willing to adopt NVIDIA’s tightly coupled rack-scale platform in exchange for bandwidth and density. Buyers prioritizing x86 compatibility or more conventional server modularity may instead consider HGX Rubin NVL8 or cloud access. Partner systems—not ordinary retail boards—are the relevant availability path for the second half of 2026.
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Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
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