Short answer: Hyper-NA EUV is a possible successor to ASML’s 0.55-NA High-NA EUV, not an announced commercial product. Public industry discussions have considered numerical apertures around 0.75–0.85, but ASML’s documented production roadmap remains focused on making High-NA EUV manufacturable, with customer insertion targeted for 2027–2028.
What Hyper-NA EUV means today
Extreme ultraviolet (EUV) lithography uses 13.5-nanometer light to project circuit patterns onto a photoresist-coated wafer. ASML’s current production EUV systems use a numerical aperture (NA) of 0.33. Its next-generation EXE platform raises that to 0.55, the generation commonly called High-NA EUV.
Hyper-NA is a name for a possible later step beyond 0.55 NA. Imec has discussed a future range of approximately 0.75–0.85 NA and the possibility of printing line-space pitches well below 20 nanometers. That is a roadmap concept, not a finalized ASML specification. No public source establishes a Hyper-NA product name, confirmed customer, launch year, price or high-volume-manufacturing schedule.
ASML makes the scanners; it does not manufacture finished chips. Semiconductor companies such as Intel, Samsung and TSMC operate the tools, while specialist partners including Carl Zeiss SMT supply critical optical components. ASML describes Zeiss as a strategic supplier in its financial strategy.
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Why numerical aperture matters
NA describes how much light an optical system can collect and how finely it can resolve a pattern. A simplified relationship is:
Resolution ≈ k1 × λ ÷ NA
Here, λ is the 13.5-nanometer wavelength and k1 represents process and imaging factors. Holding wavelength constant, increasing NA can improve resolution. The cost is a shallower depth of focus and tighter requirements for optics, wafer flatness, alignment, focus control and process stability.
EUV scanners use multilayer mirrors rather than transmissive lenses because most materials absorb EUV light. The mirrors operate in a vacuum and must be extraordinarily smooth; ASML says its largest mirrors are roughly one meter across and polished to smoothness on the order of tens of picometers. See ASML’s optics explanation.
Where conventional EUV, High-NA and Hyper-NA fit
| Generation | Approximate NA | Status and role |
|---|---|---|
| Conventional EUV (NXE) | 0.33 | Established high-volume EUV foundation |
| High-NA EUV (EXE) | 0.55 | Current next-generation platform; ASML cites approximately 8-nanometer resolution |
| Hyper-NA concept | Approximately 0.75–0.85 in public imec discussion | Possible longer-term successor; no finalized commercial product publicly verified |
ASML’s product information says the 0.55-NA EXE platform uses new optics and faster stages and is intended to support advanced logic beginning around the 2-nanometer class and later memory generations. Its EUV overview is at ASML’s EUV systems page. Node labels are process-generation names, not literal statements that every printed feature measures exactly 2 or 1.4 nanometers.
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High-NA’s near-term value is process simplification. A higher-NA exposure can print tighter patterns that otherwise might require several multipatterning exposures. Reducing those steps can lower mask count, overlay risk, defect opportunities and cycle time on selected layers. It does not mean an entire chip is exposed with High-NA.
ASML delivered its first High-NA system in December 2023. ASML and imec subsequently opened a joint laboratory where chipmakers and suppliers can work with a prototype scanner, resist processing and metrology equipment (joint-lab announcement). Imec announced arrival of an EXE:5200 system on March 18, 2026 (imec announcement).
In its January 2026 presentation, ASML said eight High-NA systems had shipped by the end of 2025, six were operating and a second-generation EXE:5200B was running at a customer site. The company targeted high-volume-manufacturing requirements by the end of 2026 and customer insertion in 2027–2028 (presentation).
ASML’s July 2026 investor-call transcript said Intel was using High-NA EUV on a subset of its 18A process to produce selected Core Ultra Series 3 processors. That is a production-environment milestone, not evidence that every layer of a mass-produced processor uses High-NA (transcript).
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If 0.55-NA tools eventually reach their practical limits, a 0.75–0.85-NA system could provide additional optical resolution while retaining the 13.5-nanometer wavelength. Imec’s discussion presents the possibility of pitches far below 20 nanometers without returning to extensive High-NA multipatterning (imec roadmap discussion).
- Smaller printable pitches for selected logic and memory layers.
- Fewer multipatterning exposures, masks and process steps in suitable designs.
- Additional options for transistor, interconnect and memory scaling.
- Potentially lower process complexity if the scanner’s cost is offset by simpler patterning.
These are potential benefits, not demonstrated commercial outcomes. A higher NA only matters if the full process prints acceptable wafers repeatedly and economically.
The engineering barriers
Depth of focus and wafer topography
Higher NA narrows the focus window. Film-thickness variation, wafer topography, stage motion and focus drift therefore have a larger effect on yield. A tool can resolve a test pattern yet fail to maintain that performance across a production wafer.
Optics, thermal control and alignment
High-NA already requires complex mirror designs and precise thermal and mechanical control. Hyper-NA would make mirror fabrication, alignment and aberration correction more demanding. ASML’s existing optical requirements illustrate the scale of the challenge (optics and mirrors).
Anamorphic imaging and masks
High-NA EUV uses anamorphic imaging, with different reduction ratios by direction. That optical approach helps manage the system but changes exposure-field and mask-design constraints. Die size, stitching and productivity consequences must be solved in the actual architecture; public material does not establish a final Hyper-NA mask design.
Resists and stochastic defects
At very small dimensions, random photon and material effects can produce line-edge roughness, missing contacts or bridged lines. The patterning stack must balance resolution, sensitivity and roughness while controlling outgassing, contamination, mask defects, etch transfer, inspection, overlay and metrology.
Source power and throughput
A scanner must expose wafers fast enough to justify its capital cost. ASML reported a 1,000-watt EUV-source demonstration in its 2025 annual-report material, but source power is not the same as commercial wafer throughput. Dose, uptime, contamination, maintenance and resist behavior also determine cost per wafer (annual-report material).
Economics
High-NA tools are substantially more complex than conventional EUV systems. ASML does not publish a standard list price on the cited product pages, and no official Hyper-NA price exists. The business case would compare scanner and infrastructure costs with the masks, cycle time, yield losses and overlay risk of continued multipatterning.
Does Hyper-NA extend Moore’s law?
It could extend geometric scaling, but lithography alone cannot preserve every historical benefit associated with Moore’s law. Future chips also depend on gate-all-around nanosheets, backside power delivery, complementary FET (CFET) stacking, interconnect materials, memory architecture, advanced packaging and design-technology co-optimization. Imec’s CMOS-scaling overview treats these as a coordinated system problem (imec CMOS scaling).
A smaller printed pitch does not automatically produce a faster, cheaper or more energy-efficient processor. Yield, wiring resistance, power delivery and package-level bandwidth can dominate the final product.
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Potential early users include leading-edge logic manufacturers, advanced DRAM producers, research consortia such as imec, and suppliers of resists, masks, inspection and metrology. Those are likely users by industry role, not confirmed Hyper-NA customers.
High-NA adoption is already differentiated. Intel has disclosed production-environment use on selected 18A layers. Samsung has acquired High-NA equipment for research while weighing production economics, and TSMC has been more cautious about immediate insertion, according to reporting by Tom’s Hardware. None of that establishes a Hyper-NA purchase order or production commitment.
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Milestones that should not be confused
- Installed: the tool has arrived at a site.
- Accepted or qualified: equipment or a process meets a defined customer test.
- Production-ready: the process is prepared for manufacturing requirements.
- High-volume manufacturing: wafers are produced at sustained commercial scale.
What happens if Hyper-NA is delayed?
Keep using 0.33-NA EUV with multipatterning
The installed base and mature ecosystem reduce immediate capital risk, but extra masks and exposures increase overlay, defect, cycle-time and cost pressure.
Use 0.55-NA selectively
Fabs can reserve High-NA for the tightest-pitch layers while retaining conventional EUV or DUV elsewhere. This avoids an all-at-once transition.
Make low-NA EUV faster
ASML said its NXE:3800E could reach 230 wafers per hour after upgrades and described a longer-term low-NA target of at least 330 wafers per hour at the start of the next decade (Q1 2026 transcript). A faster mature platform can remain economically attractive even when High-NA offers better single-exposure resolution.
Change the device and package
Gate-all-around transistors, backside power, chiplets, hybrid bonding, 3D stacking and larger advanced packages can improve system performance without requiring every feature to be printed at the smallest possible pitch.
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Quick Recap
How to judge a future Hyper-NA claim
- Does the proposed NA deliver a meaningful gain over 0.55 NA on real production layers?
- How many multipatterning steps does it remove?
- Can throughput, uptime and overlay meet fab economics?
- Do masks, resists, inspection and metrology support acceptable yield?
- Does cost per wafer beat the alternatives?
- Is the evidence a laboratory result, an installed tool, a qualified process or sustained high-volume production?
Timeline: documented progress versus possibility
| Date | Milestone |
|---|---|
| December 2023 | ASML delivered its first High-NA EUV system. |
| 2024 | ASML and imec opened a joint High-NA development laboratory. |
| End of 2025 | ASML reported eight High-NA systems shipped, six operating and an EXE:5200B at a customer site. |
| March 18, 2026 | Imec announced receipt of an EXE:5200. |
| July 2026 | ASML described selected Intel 18A layers using High-NA in a production environment. |
| 2027–2028 target | ASML’s stated expectation for High-NA customer insertion. |
| Beyond High-NA | Imec has publicly discussed Hyper-NA around 0.75–0.85 NA; no commercial timetable is established. |
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