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ASML’s nearly $2 billion program announced in 2016 was a long-term bet on the optics behind the next generation of extreme ultraviolet lithography. Most of the reported amount went toward a 24.9% stake in Carl Zeiss SMT and a six-year commitment to equipment and other needs; the effort helped prepare the companies for High-NA EUV, now in high-volume manufacturing at Intel Foundry on selected layers.
What did ASML spend the nearly $2 billion on?
In 2016, ASML announced a program with Carl Zeiss SMT, the supplier of the precision optics used in its lithography systems. EE Times reported the overall commitment as nearly $2 billion. The reported components were:
| Reported component | Amount and purpose |
|---|---|
| Zeiss SMT stake | About $1.1 billion in cash for a 24.9% stake in the Zeiss subsidiary, as reported by EE Times in 2016. |
| Joint research and development | About $244 million as a one-time contribution to a joint R&D project, as reported by EE Times in 2016. |
| Equipment and other needs | Another $600 million over six years for capital equipment and other needs, as reported by EE Times in 2016. |
Those rounded figures total about $1.944 billion, which accounts for the “nearly $2 billion” description. The stake was not a purchase of all of Zeiss SMT: it gave ASML an indirect 24.9% interest in the subsidiary. ASML’s investor materials described that interest as a way to support further EUV development and align the companies’ long-term roadmaps, including High-NA.
What is High-NA EUV, and how does it differ from established EUV?
EUV lithography uses light with a wavelength of 13.5 nanometers and mirrors to project a photomask pattern onto a silicon wafer. Numerical aperture, or NA, describes how much of the light’s angular range the optical system can collect. High-NA systems collect light over a larger range than established EUV, which improves the system’s ability to resolve smaller features but requires much larger optics.
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| Characteristic | Established EUV | High-NA EUV |
|---|---|---|
| Numerical aperture | 0.33, according to ZEISS’s current technical overview. | 0.55, according to ZEISS’s current technical overview. |
| Optical resolution | Not stated in the cited ZEISS overview. | Below 10 nanometers, according to ZEISS. |
| Optical system | Not stated in the cited ZEISS overview. | The projection optics contain more than 40,000 parts and weigh about 12 tons; the illumination system weighs about six tons, according to ZEISS. |
| Photomask format | Current production options include 6-inch masks, according to Intel. | ASML and TSMC are coordinating a longer-term transition to 12-inch masks; their announced targets are described below. |
ZEISS says the higher aperture enables around three times more structures on the same area. That is an optical capability, not a guarantee that every chip will gain that density: mask design, process integration and manufacturing choices also matter. For leading-edge logic and memory, the potential benefit is finer patterning and fewer process steps, if the surrounding process and design ecosystem can support it.
Why the optics make the investment significant
High-NA is not simply an existing scanner with a stronger lens. ZEISS describes mirrors manufactured to atomic precision that take about a year to make. The company measures them repeatedly in a vacuum-chamber system roughly five by ten meters in size and weighing about 150 tons. ZEISS says about 2,000 of its SMT employees work on High-NA EUV. These demands help explain why ASML’s commitment involved both an ownership stake in a key supplier and funding for development and equipment.
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“The mirrors of High-NA-EUV lithography are unique in size and precision. Therefore we’ve developed a completely new system design,” said Dr. Peter Kürz, head of the High-NA-EUV lithography field of business at ZEISS SMT.
Why did ASML take a stake in Zeiss SMT?
The arrangement connected ASML more closely to the company responsible for critical optics as the two worked toward a more demanding scanner generation. ASML’s investor materials characterized the indirect stake as support for continued EUV development and alignment on long-term roadmaps, including High-NA. It was a strategic supplier relationship as well as a financial investment: the success of ASML’s future scanners depended in part on advances in Zeiss optics and metrology.
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At the time, the size and unusual nature of the commitment drew attention. Risto Puhakka, then president of VLSI Research, told EE Times in 2016 that ASML had not previously taken a direct investment stake with a supply-chain company and called the move evidence of both the risk involved and ASML’s confidence in the new systems. That confidence did not remove the technical and commercial risk; it tied ASML more closely to a long development path.
When did High-NA EUV reach production?
The 2016 report said systems with NA above 0.5 would not be ready for volume production until about 2024. That was an anticipated milestone, not a promise that all customers or chip layers would switch at once. The status reported in September 2026 shows a staged adoption:
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Intel: selected layers in high-volume manufacturing
In a September 8, 2026 release, Intel and ASML said High-NA EUV was being used in high-volume manufacturing at Intel Foundry. They reported more than one million wafers processed across certification, testing, R&D and volume production combined; the figure does not mean that all those wafers were high-volume product wafers. The companies identified selected layers of Intel Core Ultra Series 3, also known as Panther Lake, as made using High-NA. ASML’s CEO said Intel had installed the first commercial EXE system in 2024 and had gone on to qualify newer tools and ship the first high-volume logic product manufactured with High-NA.
TSMC: future adoption and a mask transition
ASML and TSMC said on September 8, 2026 that TSMC intends to use High-NA in high-volume manufacturing for advanced nodes starting in 2030. Their large-format photomask initiative targets a 12-inch mask pilot line by 2031 and 12-inch High-NA lithography systems entering advanced-node production by 2033. These are announced targets and intentions, not evidence that the milestones have already occurred.
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The mask transition matters because scanner performance is only one part of production readiness. Masks, stitching, automation, electronic-design-automation tools, materials and fab processes all need to work together. Intel’s reported current production options use 6-inch masks, while the TSMC-ASML initiative addresses a later 12-inch format intended to support scanner productivity.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the investment means for chipmakers and investors
The program’s significance is best understood as an investment in a capability and its supply chain, not as a standalone purchase of a machine. Higher resolution can give chipmakers another way to pattern smaller features and may reduce the number of process steps needed for some layers. But those benefits depend on the economics and readiness of the entire manufacturing process, including masks and fab integration. The Intel and TSMC timelines illustrate that adoption differs by customer and that a scanner generation can move from development to selected production use before it becomes a broadly deployed industry standard.
For investors assessing the business implications, the 2016 commitment signals how much strategic value ASML placed on its optics partnership and the next EUV roadmap. It does not, by itself, establish the financial return on the investment, the cost of High-NA tools to customers, or how quickly all chipmakers will adopt them. The clearest evidence of progress is operational: Intel and ASML reported selected-layer high-volume use in 2026, while TSMC’s stated start for advanced-node high-volume use remains 2030.
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