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Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →Repair Windows errors before they cause bigger problemsFix Now →TSMC’s leading-edge capacity is tight, but the company has not publicly confirmed that its 3nm and 5nm operations are each running at exactly 100% utilization. Its latest disclosures show strong demand, a rising contribution from 3nm, and higher overall capacity utilization—not a node-by-node utilization figure. For investors and supply-chain watchers, the distinction matters: “fully booked” is not the same as a verified 100% physical operating rate.
What TSMC’s latest figures actually show
In its second-quarter 2026 reporting, TSMC said 3nm accounted for 30% of wafer revenue and 5nm for 33%. Technologies at 7nm and below together represented 77% of wafer revenue. Those figures establish the economic importance of advanced manufacturing, but revenue share is not a measure of how much of a node’s capacity is in use. TSMC Q2 2026 management report
| Measure | Q2 2026 disclosure | What it means |
|---|---|---|
| 3nm share of wafer revenue | 30% | Revenue contribution, not utilization |
| 5nm share of wafer revenue | 33% | Revenue contribution, not utilization |
| 7nm and below share of wafer revenue | 77% | Combined advanced-node revenue contribution |
| HPC share of net revenue | 66% | Platform mix, not a wafer-capacity measure |
TSMC also attributed part of its Q2 gross-margin improvement to a higher overall capacity-utilization rate. It did not publish separate utilization percentages for N3, N5, or individual fabs. The company reported Q2 revenue of US$40.20 billion and a gross margin of 67.7%, but neither figure independently establishes a 100% operating rate for any node. TSMC Q2 2026 quarterly results
Why “100% capacity” is difficult to verify
The phrase can refer to several different things, and headlines often blur them:
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- Utilization compares actual production with a defined measure of available or rated capacity. The result depends on the period and the capacity definition.
- Fully booked means customer commitments use all capacity available for allocation. A fab can be fully booked without operating at precisely 100% of rated physical capacity.
- Nominal capacity is an assumed or theoretical output figure. Effective capacity reflects practical constraints such as maintenance, engineering runs, product mix, yield, and bottlenecks.
- Revenue mix shows how much revenue a technology contributes. It does not reveal the number of wafer starts or the percentage of available tools in use.
A credible 100% claim should specify who made it, the period measured, the exact process variant and fab locations covered, and whether the figure refers to bookings, wafer starts, completed wafers, or sellable chips. Without those details, it should be treated as an estimate or an ambiguous shorthand—not as TSMC-confirmed guidance.
What confirms that capacity is under pressure
Although TSMC has not verified exact 3nm and 5nm utilization, its public statements do support the narrower conclusion that leading-edge capacity is tight. In its Q1 2026 earnings transcript, the company described capacity as tight, cited a robust multiyear pipeline for 3nm technologies, and said it was increasing global 3nm capacity in response to strong AI demand. It also described flexible capacity support across the N7, N5, and N3 families. TSMC Q1 2026 earnings transcript
TSMC’s Q2 revenue mix also shifted toward 3nm: the node’s share of wafer revenue rose from 25% in Q1 to 30% in Q2, while 5nm’s share fell from 36% to 33%. That is a change in revenue mix, not proof that 3nm utilization is higher than 5nm utilization. Node-level utilization data would be needed to make that comparison.
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Why demand for advanced nodes is strong
AI is a major source of demand, but it is not limited to GPU accelerators. Advanced-node work can include custom AI ASICs, high-performance computing processors, networking silicon, CPUs, and other components used in data centers. TSMC’s Q2 2026 platform mix reflects the importance of computing: HPC supplied 66% of net revenue, while smartphones supplied 22%. IoT accounted for 5%, automotive 4%, digital consumer electronics 1%, and other platforms 2%. These are company revenue shares, not estimates of how many wafers each platform consumes. TSMC Q2 2026 management report
Smartphone application processors and premium consumer processors also compete for advanced manufacturing resources. HBM base dies and other related components can add demand, while products that combine logic with advanced packaging may face constraints beyond wafer fabrication. Packaging capacity, HBM, substrates, testing, and board assembly can all affect how many finished systems reach customers; available wafers alone do not guarantee a complete AI chip supply.
Why TSMC is converting some 5nm tools for 3nm
TSMC said it was converting some 5nm tools in Taiwan to support 3nm output. The N3 and N5 families share aspects of the company’s leading-edge manufacturing infrastructure, allowing some equipment and capacity planning to be adapted across generations. Reusing or optimizing tools can help add N3 output sooner than waiting for an entirely new fab to be built and ramped.
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That decision is evidence of a specific capacity response to N3 demand; it does not prove that N5 is at exactly 100%. Depending on which tools are converted and how production is balanced, the change could also limit N5 capacity at the margin. TSMC’s process families are not single interchangeable pools: variants have different design rules, libraries, qualification needs, and customer schedules.
What “3nm” and “5nm” mean for customers
These are process-generation names, not literal measurements of a transistor’s dimensions. TSMC’s N3 family includes multiple variants and enhancements, while N5 has related derivatives such as N4-class technologies. TSMC’s annual-report materials describe these as families of advanced process technologies rather than one uniform product per label. TSMC 2025 annual-report technology overview
A customer seeking a particular variant, design-rule set, or performance target may face a different availability picture from another customer using a related process. Wafer starts, completed wafers, usable dies after yield, and packaged chips are also different measures of supply. Consequently, a broad statement about “3nm capacity” can hide meaningful differences in variant, fab, and production stage.
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Where additional 3nm capacity is planned
TSMC’s Q1 2026 transcript described planned capacity additions. These are future production plans, not capacity available in August 2026:
| Location or action | Plan and stated timing |
|---|---|
| Tainan, Taiwan | A new 3nm fab in the GIGAFAB cluster; volume production scheduled for the first half of 2027 |
| Arizona, United States | TSMC’s second Arizona fab is planned for 3nm; volume production scheduled for the second half of 2027 |
| Japan | The second fab is planned for 3nm; volume production scheduled for 2028 |
| Tainan, Taiwan | Some existing 5nm tools are being converted to support 3nm output |
TSMC’s managed manufacturing facilities exceeded 17 million 12-inch-equivalent wafers of annual capacity in 2025, according to the company’s fab-capacity information. That is a company-wide figure across its manufacturing footprint, not a disclosure of N3 or N5 capacity. TSMC fab-capacity information
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What tight capacity could mean for chip buyers and investors
When a sought-after process is constrained, the practical effects can include longer lead times for new customers, greater value in long-term capacity reservations, and possible premiums for incremental capacity. Those are potential market effects, not confirmation of a specific TSMC price increase or of a shortage affecting every customer. TSMC says it is expanding and flexibly optimizing capacity to support customer growth; tight conditions do not establish that all orders are being refused.
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- For chip companies: capacity planning and early process qualification matter. Moving a design to another foundry can require changes to the process design kit, IP, packaging approach, and validation schedule, so an alternative is not necessarily a quick substitute.
- For investors: higher utilization can support revenue and margins, while new fabs, tool conversions, overseas ramps, and yield learning require investment and can pressure margins. Capacity expansion also carries the risk of overbuilding if demand later weakens.
- For end markets: a tight advanced-node segment does not automatically mean a broad consumer-chip shortage. The effect depends on which products need a constrained process and whether packaging, memory, testing, or other inputs are also available.
Foundry alternatives should be assessed for the particular product rather than treated as interchangeable. Samsung Foundry is an advanced-node alternative, but availability, yields, design ecosystem, and schedules must be evaluated project by project. Intel Foundry may matter for customers seeking a U.S.-based manufacturing relationship, but it should not be assumed to be a drop-in replacement for current TSMC N3/N5 production. GlobalFoundries and UMC are more relevant to many specialty, mature-node, RF, automotive, or connectivity designs than to leading-edge AI logic. A switch can entail redesign, qualification, and ecosystem costs.
TSMC does not publish standard public wafer prices or a simple self-service route to reserve leading-edge production. Commercial engagement generally requires a foundry relationship, design work, process qualification, and capacity planning. The company’s foundry services information and customer portal provide official starting points, but neither constitutes a public capacity quote.
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