The Tool Desk
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What Tesla presented at Hot Chips 34
HC34 means Hot Chips 34, the 2022 semiconductor and computer-architecture conference. Tesla’s program included sessions on Dojo’s microarchitecture and system scaling, as well as a keynote on system integration. The conference program lists the sessions and speakers: Hot Chips 34 program.
Tesla described Dojo as an in-house supercomputer for machine-learning training, designed to scale and adapt to different algorithms while focusing on Tesla’s own requirements. The microarchitecture presentation is available in Tesla’s HC34 slides. Dojo was not presented as a retail accelerator or general-purpose cloud service.
Why build a system around training video models?
Tesla’s stated use case centered on neural networks for autonomy. Training systems must do more than perform matrix operations: they also need to ingest and process training data, move it to compute units, synchronize work across those units and keep the system supplied with memory bandwidth. For video-heavy workloads, the data pipeline can be a significant part of the design problem.
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Tesla’s argument was therefore a system-level one. It designed compute, memory, networking, host interfaces, packaging, power and cooling around its intended workloads rather than treating Dojo as simply a collection of accelerator chips. Tesla’s public overview of its AI work is at Tesla AI and Robotics.
How Dojo’s architecture was organized
From compute die to system
Tesla presented a hierarchy of CPU → die → module → board → rack → cabinet → system. In general, communication tends to become slower and more constrained as it crosses farther-out levels of a system. Dojo’s design sought to keep important communication close to its compute fabric while still allowing the system to expand.
It is important to distinguish three levels. A D1 die was a custom compute chip; a training tile combined multiple D1 dies into a module; and the Dojo system encompassed many tiles plus interface processors, hosts, networking, memory, storage, software, power and cooling. The design drew on system-on-wafer ideas, but describing the deployed architecture simply as “a wafer” obscures its modular organization.
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The 25-die training tile
Tesla’s later Hot Chips material describes a training tile made from a 5×5 array of 25 D1 chips. The tile integrated power delivery, cooling and mechanical and electrical connections, and was intended to link directly with neighboring tiles. Tesla’s presentation listed 15 kW for tile power delivery; that is a tile figure, not the power consumption of an entire Dojo system. See the Tesla TTPoE presentation.
How tiles communicated: TTP and Ethernet
Tesla’s proprietary Tesla Transport Protocol (TTP) was designed for communication across the high-performance Dojo fabric. Tesla’s presentation listed approximately 4.5 TB/s of off-tile bandwidth per edge. These are company-disclosed design figures, not independent measurements of end-to-end model-training performance.
Custom protocol did not mean Ethernet was absent. Tesla also described TTP over Ethernet (TTPoE), using Ethernet infrastructure to extend the fabric. In its 2024 presentation, Tesla characterized TTPoE as a lossy, exascale fabric intended to reduce complexity and software overhead associated with traditional lossless fabrics. The practical idea was to combine specialized communication inside the system with Ethernet-based scale-out.
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What the Dojo Interface Processor did
The Dojo Interface Processor was a custom PCIe card connecting host systems to training tiles. Tesla’s later presentation listed 32 GB of high-bandwidth memory, approximately 800 GB/s of memory bandwidth, a 900 GB/s TTP interface and a 32 GB/s PCIe Gen4 interface. These are Tesla’s presentation specifications, not independent benchmark results.
ServeTheHome reported that a first-generation host could use up to five interface cards, for up to 4.5 TB/s of aggregate bandwidth to training tiles. The interface processor helped separate the compute fabric from host-side work, including data loading and video ingestion. That separation matters because a training workload can be constrained by getting data ready and delivered, not only by the accelerator’s arithmetic capacity. See ServeTheHome’s HC34 report.
Scaling beyond a tile—and feeding the compute
ServeTheHome reported that Tesla presented an exascale design capable of scaling to approximately 3,000 accelerators and planned “Exapod” units containing 120 tiles. These were presented plans, not evidence that Tesla operated a full 3,000-accelerator configuration at HC34. The proposed system was also disaggregated: compute, memory and input/output resources could be expanded separately.
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Tesla’s TTPoE material described “Mojo” hosts for variable input ingestion, separation of forward-pass data ingestion from backward-pass all-reduce traffic, and the ability to add processing capacity for video or data loading independently. The intent was to present a more uniform system view across compute and communication while allowing data-pipeline resources to scale with need. These details help explain why Dojo was more than a custom chip or a tile-to-tile bandwidth figure: its pitch depended on coordinating data movement and computation.
How the HC34 concept differed from a conventional GPU cluster
| Area | Conventional GPU cluster | HC34 Dojo concept |
|---|---|---|
| Compute | Commercial GPUs with host CPUs | Tesla-designed D1 compute dies |
| Packaging | GPU servers connected through a network fabric | Modular training tiles with integrated power and cooling |
| Interconnect | Often Ethernet, InfiniBand or vendor-specific links | TTP for the specialized fabric, with TTPoE for Ethernet-based extension |
| Scaling unit | Commonly a server, GPU node or rack | Tiles, interface processors and hosts, assembled into larger systems |
| Workload emphasis | Broad AI and HPC workloads | Video-heavy Tesla autonomy training, with flexibility claimed for other algorithms |
| Memory approach | GPU memory plus host and system memory | Emphasis on on-chip SRAM alongside HBM on interface processors |
| Availability | Commercial systems and cloud instances are available from vendors | No evidence that Dojo was sold as a standalone commercial system |
The comparison describes design approaches, not a performance ranking. High theoretical bandwidth does not establish higher training throughput, and HC34 did not provide an apples-to-apples independent benchmark proving that Dojo was faster, cheaper or more efficient than NVIDIA-based systems.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the disclosed numbers do—and do not—show
Terms such as “exascale” need context. An aggregate operation-rate figure depends on precision and workload assumptions; it does not automatically mean a system achieved a particular general-purpose supercomputer ranking. Tesla’s later TTPoE presentation also described a 4× exaflop BF16/FP16 engineering system. That later engineering-system figure should not be read as proof of production performance or confused with the HC34 scaling plan.
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- A D1 die, a 25-die training tile and a full system are different units; a figure for one cannot be applied to another.
- Bandwidth specifications describe potential data movement, not measured end-to-end model-training speed.
- The public HC34 material establishes what Tesla presented, but does not by itself verify that every planned configuration reached production.
- Dojo was primarily framed as a training system. It should not be conflated with Tesla’s automotive inference chips or later AI5 and AI6 discussions.
What happened to Dojo after HC34?
The original HC34 architecture and the later Dojo 3 effort are not interchangeable. Bloomberg reported in August 2025 that Tesla disbanded the Dojo team. In January 2026, Bloomberg reported that Elon Musk said work on Dojo 3 would restart after progress on AI5: Bloomberg’s August 2025 report and Bloomberg’s January 2026 report.
Tesla’s Q1 2026 investor materials said Cortex 2 was online and running training workloads while the company continued custom-silicon development with Dojo 3 to reduce training costs. The filing places Dojo within a broader compute strategy; it does not establish that the 2022 D1-based design remained Tesla’s sole or dominant training platform. See Tesla’s Q1 2026 investor update filed with the SEC.
Why Dojo’s engineering ambition carried risks
Custom silicon can be attractive when a company has a distinctive workload and enough scale to justify tailoring hardware to it. But a custom system also requires coordinated investment in chips, packaging, networking, software, power and cooling. A design that looks compelling at tile level can encounter software, synchronization, thermal, reliability or data-ingestion challenges at cluster scale.
The approach also creates software and supply-chain dependencies. Compilers, kernels, libraries, scheduling, debugging and model-porting tools must support the architecture; advanced manufacturing, packaging, HBM and power-delivery components must be available. Those execution demands, combined with fast-moving AI workloads and commercial accelerators, are part of the context for Dojo’s changing status after 2022.
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