Niobium announced a $5.5 million seed round on May 7, 2024, and by June 5 its first fully homomorphic encryption (FHE) accelerator had reached tape-out. That was a significant development milestone, not a product launch: the design still needed fabrication, testing, packaging and integration. The company’s large performance estimates were claims, not independently verified results in the cited coverage.
What Niobium announced
The Dayton, Ohio-based startup said Fusion Fund led its $5.5 million seed round, with Morgan Creek Capital, Rev1 Ventures, Ohio Innovation Fund and Hale Capital also participating. The announcement also named Fusion Fund partner and former Hewlett-Packard CTO Shane Wall to Niobium’s board. Niobium’s May 7, 2024 funding announcement described the financing as support for commercializing an FHE accelerator.
Separately, EE Times reported on June 5, 2024, that Niobium had taped out its first FHE chip. The financing and tape-out were related parts of the company’s development effort, but they were not the same event: the funding was capital for the business and commercialization work, while tape-out marked submission of a chip design to a foundry for fabrication.
What fully homomorphic encryption does
FHE lets a processor perform computations on encrypted data. A customer encrypts data before sending it to a cloud service or accelerator; the service processes ciphertext and returns an encrypted result for the customer, who holds the decryption key. In principle, the computing provider need not see the underlying data in plaintext while carrying out the computation.
#1 Best Overall
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
That differs from encryption at rest or in transit, which protects stored data or data moving between systems but ordinarily requires decryption for processing. It also differs from a trusted execution environment (TEE): a TEE processes decrypted data inside a protected hardware environment, so security depends in part on the processor and platform’s protections and trust model.
FHE does not remove every privacy or security risk. It does not, by itself, secure decryption keys, compromised endpoints, application logic, access controls or implementation flaws. Metadata, traffic patterns, query frequency and outputs may also reveal information. Organizations still need sound key management, identity controls, conventional encryption, auditing and system security.
Why FHE hardware matters
FHE is mathematically workable, but its computational cost has been a barrier to practical use. Many workloads require substantial polynomial and modular arithmetic, ciphertext transformations, and bootstrapping or other noise-management operations. CPUs can perform these tasks, but they were not designed specifically for the highly parallel operations involved.
Niobium’s argument was that specialized hardware could accelerate those operations enough to make more encrypted-computing workloads practical. EE Times described its design as DSP-like, with many multiply-accumulate (MAC) units and a proprietary instruction set architecture. The commercial question is not simply whether a chip can make a calculation faster; it is whether the complete workload can run at a useful cost, speed and level of developer effort.
Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
What was known about the first chip
In its June 2024 report, EE Times described the planned accelerator as a PCIe card for installation in existing cloud servers, built on GlobalFoundries’ 12-nanometer low-power process. The article reported a parallel, DSP-like architecture with MAC units and a proprietary ISA. Niobium said the software stack was intended to address four broad FHE scheme categories.
Those are design and development details, not a complete product specification. The cited coverage did not establish the chip’s transistor count, clock speed, power consumption, memory bandwidth, die size, measured throughput or latency. It also did not report independently reproduced application benchmarks.
Tape-out means the design was sent to the foundry. It does not establish that the first silicon worked as intended, met power or frequency targets, or was ready for customers. Fabrication, bring-up, validation, packaging, PCIe-card integration, driver and compiler work, benchmarking and customer qualification remained relevant steps.
What “support for four FHE schemes” means
Niobium’s reported target was coverage across four broad categories of FHE workloads, not support for every possible FHE scheme or implementation. The categories described included binary operations associated with TFHE-style workloads, approximate arithmetic associated with CKKS and encrypted AI, and two exact-arithmetic categories. FHE has multiple schemes, variants and parameter choices; a claim about four categories should not be read as universal compatibility.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
Rank #3
- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
- [Onboard Debugger ] Sipeed Tang Nano 20K Development Board support JTAG for FPGA, USB to UART for FPGA,USB to SPI for FPGA communication, Control MS5351 generate frequency
- [USB2.0 HS interface] The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.Support Serial communication, high-speed SPI reception.
- [Application scenarios] Tang Nano 20K Open source Development Board supports game console emulators, drives RGB screens, multiple display outputs, 20K LUT4, RISC-V soft-core experiments.
- [Wiki] "dl.sipeed.com/shareURL/TANG/Nano_20K/1_Datasheet";Any after-Sales Privems, Please Contact us by click "Waypondev" store and ask a question or leave the message in our forum by "forum.youyeetoo .com/".
Scheme support, application readiness and end-to-end performance are separate questions. A chip might support a scheme in principle yet require software adaptation for a particular library or application. Nor does support across categories show that each workload receives the same speedup. A buyer would need evidence for its own scheme, security parameters and use case.
How to read Niobium’s speed claims
Niobium told EE Times that the first chip could improve FHE performance by roughly 1,000× to 5,000× compared with standard CPUs. Its funding announcement described a possible gain of up to four orders of magnitude. These were company-reported expectations, not independently verified benchmark results in the cited coverage. The word “up to” also does not describe typical performance.
A speedup figure is difficult to interpret without the comparison details. Results can vary with the CPU baseline, software library, FHE scheme, security level, precision, batch size and workload. A chip may accelerate arithmetic kernels while leaving data movement, bootstrapping, encryption, scheduling or application logic as bottlenecks. A fast kernel is not necessarily a fast end-to-end application.
To assess such a claim, enterprise buyers and investors would want matched comparisons against CPUs, GPUs and other accelerators, using production-relevant security settings and real workloads. They would also need power use, total system cost, programming requirements and cost per encrypted query or inference. The cited 2024 coverage did not supply those results.
Do these 3 things before closing this tab:
1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsRank #4
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
- Works with Verilog and VHDL: No matter which programming language you want to get started with, the Go Board will work for you!
- No extra device required: Simply plug the Go Board into a USB port and go! Getting started with FPGAs has never been easier.
- Works with all operating systems: Windows, Mac, Linux
Where the seed money and government support fit
Niobium said the seed proceeds would support software engineering, compiler optimization, application development, customer engagement, early access, intellectual-property protection and future hardware optimization. EE Times also reported significant non-dilutive government support for FHE hardware development and linked Niobium’s work to DARPA’s Data Protection in Virtual Environments (DPRIVE) project.
Government-backed research and private venture financing are different forms of support: the former funds development under public programs, while the seed round brought private investment into the company. The cited sources do not provide a complete accounting of government contract values, ownership terms, milestones or the exact allocation of the seed proceeds.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Commercial plan and adoption hurdles
The company’s proposed targets included healthcare and pharmaceutical research, financial fraud detection, blockchain and public ledgers, digital advertising, encrypted AI training and inference, and analysis between organizations that do not want to share raw data. These were prospective use cases, not evidence in the cited coverage of production deployments or revenue.
The 2024 plan included an early-access program initially based on simulation, with hardware access planned later; Niobium expected customer pilots to begin in the fourth quarter of 2024. That was a target stated at the time, not confirmation that pilots occurred. The company also said its software stack connected with available FHE libraries and that compiler optimization would be ongoing. It anticipated relying on third-party software companies for some application-specific development.
Best Value
- Digilent Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users
For a customer, the accelerator is only one part of the equation. An FHE platform also needs compilers, runtime libraries, APIs, scheme-specific optimizations, key-management workflows, integration with cloud infrastructure, debugging tools and predictable economics. That is why Niobium’s commercial opportunity is better understood as a platform challenge than as a chip-speed contest alone.
- Technical fit: Which scheme, security parameters, precision and workload does the customer need?
- End-to-end performance: Are results measured on a real application, including data movement and bootstrapping, rather than only arithmetic kernels?
- Systems integration: How will PCIe bandwidth, host memory, orchestration, monitoring, recovery and multi-tenant isolation work?
- Developer effort: Which languages, libraries and compiler tools are supported, and how portable is the code?
- Economics and control: What is the cost per workload, who controls the decryption keys, and what happens if the customer changes hardware or provider?
Specialized hardware can create vendor dependence if software and workloads rely on a proprietary ISA or runtime. Interoperability efforts and compatibility with commonly used libraries can reduce that risk. FHE is also not always the right tool: data minimization, tokenization, differential privacy, secure multi-party computation or a TEE may be more suitable where their security and trust trade-offs fit the task.
What changed after the 2024 tape-out
Niobium’s later announcements show the company pursuing a broader encrypted-computing platform and a distinct hardware program. They should not be treated as proof that the 2024 chip achieved its projected performance.
| Date | Development | What it establishes |
|---|---|---|
| October 14, 2024 | Niobium joined the founding group of the FHE Technical Consortium for Hardware. | An industry effort around hardware and software interoperability; not a performance result for the 2024 chip. Niobium announcement. |
| February 19, 2026 | SEMIFIVE announced a design win for a later Niobium FHE accelerator program using Samsung Foundry’s 8LPU process. | A separate ASIC development effort from the 2024 GlobalFoundries 12-nm tape-out. SEMIFIVE announcement. |
| April 2, 2026 | Niobium introduced The Fog, an encrypted cloud platform. | A move toward managed infrastructure and developer access, beyond a standalone accelerator. Niobium announcement. |
| By August 18, 2026 | Niobium’s press archive reported more than $23 million in follow-on funding. | Later funding beyond, and separate from, the $5.5 million 2024 seed round. Niobium press archive. |
Niobium’s platform materials describe its current offering and architecture, including The Fog and mistic. They also characterize lattice-based FHE as believed to resist quantum attacks. That should not be read as a blanket guarantee for every scheme, parameter set, implementation or surrounding system. Public materials identified in this coverage did not establish broad availability or list pricing for The Fog; enterprise teams would need to confirm access, terms and product scope directly.
Free tools Windows power users keep installed
One-click scans. No signup required.
What investors and buyers should conclude
The 2024 funding and tape-out were meaningful signs that Niobium was attempting to move FHE acceleration from research toward commercialization. But a tape-out is not a shipping product, and the reported 1,000×–5,000× target cannot by itself establish production value. The later platform, funding and Samsung 8LPU program show continued company activity; they do not validate the earlier chip’s unverified performance claims.
For anyone evaluating Niobium, the central questions are whether its platform can run a specific workload at an acceptable end-to-end cost, whether the customer retains control of keys and data, and whether software, hardware availability and commercial terms meet operational needs. The 2024 announcement marked a milestone in that journey, not its completion.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.




