Semiconductor companies can make money from an AI chip design by selling chips or systems, licensing design IP and collecting royalties as chips ship, or selling the software and engineering services used to design and validate chips. These models can overlap. A company’s reported revenue may include much more than AI chips, so company and segment totals should not be mistaken for AI-chip-only sales.
Where revenue can enter the chip-design process
A design is not automatically a sale. A company must turn it into something a customer pays for: a licensed design, a physical chip, a system built around chips, software, or design and engineering work. The customer may be a chip manufacturer, a device maker, a cloud provider, or an integrator; the route depends on what the company sells.
| Revenue model | What the customer receives | How revenue is earned | Documented example |
|---|---|---|---|
| IP licensing and royalties | Permission to use processor or other semiconductor IP in a chip design | An access or license fee, followed by per-unit royalties when chips using the IP ship; contract terms vary | Arm |
| Chip and system sales | Processors or accelerators, sometimes combined with networking, software, and other components in a larger system | Product sales; the offering may be a component or a more integrated system | NVIDIA and AMD |
| Design software and semiconductor IP | Tools and IP used to design, simulate, verify, and implement chips | Product and maintenance revenue, including software and semiconductor-IP licensing | Cadence |
| Custom engineering and services | Specialist engineering work or customized IP | Services revenue for engineering work, custom IP, or related solutions; payment terms depend on the agreement | Cadence |
| Software around hardware | Software, libraries, APIs, SDKs, models, or specific paid software products | Some software is part of a platform; distinct products may be sold under paid licenses | NVIDIA |
How licensing and royalties work
An IP company can earn money without manufacturing or selling a finished chip. Arm reports charging customers for access to licensed designs and receiving per-unit royalties on substantially all chips shipped using its products. The royalty has typically been based on a percentage of the chip’s average selling price or a fixed amount per unit, and may rise as a chip incorporates more Arm products. Arm says licensed chips and reused platforms can generate royalties over multiple years. The actual contract determines the fees and royalty terms; there is no single rate that applies to every license.
This creates two distinct revenue events: payment for access to IP and royalties tied to later chip shipments. They should not be collapsed into one category. The license makes the design available for a customer’s product; royalties depend on the resulting chips being manufactured and shipped.
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How chip sales become system sales
A chip designer that sells products can earn revenue when its chips are purchased, but the commercial offer may extend beyond a bare component. NVIDIA describes its data-center platform as combining processors, interconnects, software, systems, and services. Customers may receive these offerings as rack-scale systems, subsystems, or modules. Its filing also describes paid licenses for NVIDIA AI Enterprise and vGPU software; that does not mean every software element in its platform is separately charged.
AMD’s Data Center segment provides a different example of a product portfolio: it includes AI accelerators as well as server CPUs, GPUs, DPUs, AI network interface cards, FPGAs, and adaptive SoCs. A segment total therefore cannot be read as revenue from one AI chip or even from AI accelerators alone. Nor should NVIDIA’s rack-scale offerings be treated as representative of every chip company: some sell components through OEMs, ODMs, integrators, or distributors rather than selling complete systems directly to customers.
Rank #2
- NVIDIA Volta GV100 Architecture — 4,608 CUDA Cores, 640 1st-Gen Tensor Cores delivering 14 TFLOPS FP32 and 112 TFLOPS deep learning performance for AI training, inference, HPC, and scientific computing workloads
- 32GB HBM2 ECC Memory — 900 GB/s Bandwidth — High-bandwidth memory on a 4096-bit bus with ECC error correction provides the memory capacity and throughput required for the largest AI models, simulations, and datasets
- PCIe 3.0 x16 Interface — 250W TDP — Standard PCIe Gen3 connectivity with passive cooling designed for enterprise rack server deployment in HPE ProLiant, Dell PowerEdge, and Supermicro platforms with adequate chassis airflow
- NVLink — Scale to 96GB Unified Memory — Connect two V100 GPUs via NVLink at 300 GB/s bi-directional bandwidth to scale GPU memory from 32GB to 96GB for larger AI training and HPC workloads
- Multi-Precision Computing — Supports FP64 (7 TFLOPS), FP32 (14 TFLOPS), FP16 (112 TFLOPS) and INT8 precision modes for flexible deployment across training, inference, and scientific simulation workloads
How design tools and engineering services earn money
Some companies earn revenue by helping customers create and validate chips rather than by selling the resulting chips. Cadence reports product and maintenance revenue that includes software and semiconductor-IP licensing, emulation hardware, and related maintenance. Its services revenue includes engineering services, fixed-fee customized IP, and cloud solutions that combine software, hardware, and services over time.
That work can span verification, digital implementation, packaging, board design, analog and mixed-signal design, and system-level design. A tool license, hardware sale or lease, maintenance arrangement, and engineering engagement are different commercial products, even when they support the same chip project.
Rank #3
- Built for Running LLMs Locally: RDNA 4, 128 AI Accelerators, up to 1,531 TOPS (INT4) for fast inference and fine-tuning
- 32GB GDDR6 VRAM for Large AI Models: 256-bit, up to 640GB/s bandwidth, run large language and multi-modal AI models without offloading
- Multi-GPU Scaling for Local AI Clusters: PCIe 5.0 and 2-slot design support dense multi-GPU builds for local AI training and inference clusters
- Diecast Shroud and Backplate: Wave-pattern design cuts memory temperature by up to 16%, keeping clocks steady during long AI training runs
- Phase-Change GPU Thermal Pad: Delivers superior thermal conductivity for consistent performance and longevity under heavy AI loads
Who manufactures the physical chips?
Designing a chip does not necessarily mean owning a fabrication plant. In its filing, NVIDIA names TSMC and Samsung as foundries used for wafer production and describes subcontractors for assembly, testing, and packaging. AMD likewise describes using third-party foundries for wafer production and external assembly, test, mark, and packaging partners. These are examples of outsourced production arrangements, not proof that every semiconductor company outsources every manufacturing stage.
In an outsourced model, the design company can commercialize its product while relying on manufacturing and packaging partners to make it. The filings establish those supplier relationships, but do not provide a universal cost structure or reveal the unit economics of an individual AI-chip design.
Rank #4
- 24GB GDDR7 ECC Memory: handles large AI, 3D and rendering files smoothly
- Powerful CUDA Compute - 8,960 CUDA cores for fast graphics and computing power
- AI & Ray Tracing Boost - Tensor of the 5th generation and RT cores of the 4th generation
- PCIe 5.0 x16 interface - fast data connection with modern systems
- 4 × DisplayPort 2.1 - Multi-monitor support for professional workflows
What reported revenue figures can—and cannot—tell you
Company financial statements help show the scale of a business and how it categorizes revenue, but a reported total does not isolate the contribution of a particular chip. These fiscal 2025 figures illustrate the difference:
| Company and measure | Reported figure | What it covers |
|---|---|---|
| AMD net revenue | $34.6 billion in fiscal 2025, up 34% from $25.8 billion in fiscal 2024 | Company-wide revenue, not AI-chip revenue. AMD’s 2025 Form 10-K |
| AMD Data Center net revenue | $16.6 billion in fiscal 2025, up 32% from $12.6 billion in fiscal 2024 | A segment including AI accelerators and other data-center products. AMD attributed the increase primarily to demand for fifth-generation EPYC processors and Instinct MI350 Series GPUs. AMD’s 2025 Form 10-K |
| AMD gross margin | 50% in fiscal 2025, compared with 49% in fiscal 2024 | Company-wide gross margin, not the margin on AI chips. AMD attributed the increase primarily to product mix and reported approximately $440 million in net inventory and related charges associated with U.S. export controls on MI308 data-center GPUs. AMD’s 2025 Form 10-K |
| AMD research and development expense | $8.1 billion in fiscal 2025, up 25% from $6.5 billion in fiscal 2024 | Company-wide R&D expense; AMD said the increase was primarily due to higher employee-related costs and headcount in support of its AI strategy. AMD’s 2025 Form 10-K |
| Cadence total revenue | $5.297 billion in fiscal 2025 | Cadence reported $4.822 billion, or 91%, from product and maintenance and $475 million, or 9%, from services. Product and maintenance includes software and semiconductor-IP licensing, emulation hardware, and maintenance—not chip sales. Cadence’s 2025 Form 10-K |
These figures also show why revenue alone does not reveal a design’s profitability. R&D expense, manufacturing arrangements, product mix, and other costs affect company results, while the cited filings do not establish the sales, royalty rate, costs, or margin for an individual AI-chip design.
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Being technically capable is only part of the commercial case. Arm lists price, performance, energy efficiency, customization, quality, software availability, support, brand recognition, and financial strength among factors on which it competes. Those criteria are useful for understanding customer choice, but they are not a universal ranking or a guarantee that a design will sell.
- For an IP business: customers must license the design, then ship products that generate royalties under their agreements.
- For a chip seller: demand must support product sales, whether customers buy components or a more integrated offering.
- For a tools or services provider: customers pay for software, IP, hardware, or expertise that supports design and validation work.
Company filings establish these business models and the reported financial categories, but they do not disclose universal royalty rates, customer-level prices, individual-design margins, or unit economics. Treating those undisclosed details as known would make comparisons between AI-chip businesses less reliable, not more precise.
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