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A foundry move is a product-specific engineering and business decision, not a simple supplier swap. Before committing, confirm that the destination process can meet the product’s requirements, that the design tools and IP are ready for it, and that qualification, yield learning, schedule, and operational visibility make the move viable—not just the quoted wafer price.
Start with product fit, not the wafer quote
Compare the candidate process against the needs of the actual product. A process that looks attractive on a headline metric may still be a poor fit if its available device options, memories, analog capabilities, voltage characteristics, or packaging choices do not support the design.
For each candidate foundry and process, document the requirements that matter to the product and ask the foundry to substantiate them with current specifications. Include performance, power, area, voltage and device options, memory and analog needs, package constraints, and any special process requirements. The available sources do not establish a neutral, process-by-process comparison, so obtain current foundry data and product-specific analysis rather than assuming one supplier’s process data predicts another’s performance.
Is the destination process ready for this design?
Design enablement is process-specific. A port may require changes to the layout, extraction, verification, and signoff flow; an existing tool flow or design rule set should not be assumed to carry over unchanged.
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- PDK and design rules: Confirm the exact process design kit version, its maturity, the current design rules, and how changes will be communicated and controlled.
- EDA tools and flows: Get the supported tool versions and formats, qualified flows, and expectations for verification and signoff. Ask how extraction and signoff results will be correlated with the destination foundry’s requirements.
- Engineering support: Establish who will resolve design-rule, tool-flow, and signoff issues, and what design services or engineering support are available.
TSMC’s 2010 announcement about interoperable EDA formats and tool qualification illustrates why design enablement needs to be checked with the destination foundry; it is not a current tool-support list: TSMC’s announcement on interoperable EDA formats.
Can the IP, libraries, and macros move?
Assess IP block by block. A block’s availability or verification status at one foundry does not establish that it is available, licensed, or qualified for the destination process and design environment.
- Check availability and qualification or assessment evidence for each required library, memory, interface, and other IP block on the destination process.
- Confirm licensing rights, any restrictions on transfer or use, and whether revalidation is required.
- Assign responsibility for integration, revalidation, and resolving failures before the port begins.
TSMC’s IP Alliance page explicitly cautions that silicon-verified IP is not guaranteed to work in every design environment or to achieve a particular production yield. Treat that as a reminder to verify the specific IP and its intended use, not as a claim about other foundries: TSMC IP Alliance.
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What qualification and reliability evidence will the product need?
Foundry process qualification and customer-product qualification are related but not interchangeable. TSMC says its new technologies undergo qualification before transfer to its fabs and describes quality and reliability systems extending into mass production. That describes TSMC’s own policy; it does not establish that every customer product is qualified or provide a universal checklist for another supplier. See TSMC’s Quality Policy.
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Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Agree with the destination foundry on the evidence required for the product’s intended use and operating conditions. The plan should identify applicable qualification requirements, reliability evidence, customer acceptance criteria, failure-analysis responsibilities, and how process or design changes will be controlled. Ask what data is specific to the destination process and what evidence, if any, applies to the actual product.
Do not compare yield or reliability claims unless the evidence is genuinely comparable—for example, it covers the relevant product, process maturity, operating conditions, and measurement basis. The sources available here do not establish independent, comparable yield or reliability results across foundries.
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Build the full cost and schedule case
Model the one-time costs and transition risks alongside recurring production economics. A lower wafer quote may not offset porting work, verification, qualification, yield learning, or a delayed time to volume.
- One-time engineering: Estimate redesign, layout changes, IP revalidation, tool-flow updates, and verification effort.
- Transition and qualification: Include masks, prototypes, qualification activity, and any packaging or test changes.
- Ramp and production: Model yield learning, production wafer economics, capacity, logistics, and the time needed to reach volume.
- Schedule exposure: Identify dependencies, decision gates, and what happens to product commitments if qualification or yield ramp takes longer than planned.
For scale—not as a foundry-move estimate—the Semiconductor Industry Association reports that the cost of designing a new chip on the latest manufacturing node rose by more than 18 times between 2006 and 2020: about $30 million for a 65nm chip in 2006 versus more than $540 million for a 5nm chip in 2020. These are historical, industry-level design-cost figures, not a forecast, transition quote, or cost for a particular product: SIA’s Chip Design and R&D page.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsNo universal cost model or schedule applies to a foundry move. Build an estimate around this product’s design, IP, process, packaging, test, qualification needs, and commercial terms.
Will manufacturing information arrive when decisions depend on it?
Agree on what operational data the team will receive, how quickly it will arrive, and what agreement governs access. Ask specifically about pilot-lot status, wafer yield, acceptance-test results, quality and reliability data, lot tracking, assembly, and shipping updates. Clarify who can act on an exception and how quickly the engineering team can get a response.
TSMC’s eFoundry page describes examples of manufacturing and collaboration information available through its services. That is an example of TSMC’s offering, not evidence that another supplier provides the same visibility: TSMC eFoundry.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Compare candidates with a decision record
Use a consistent scorecard for each candidate process. Record the evidence behind each assessment, the owner of any unresolved question, and the financial or schedule consequence if it remains unresolved. Avoid treating an unsupported estimate as equivalent to verified product-specific data.
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| Decision area | Evidence to collect | Business exposure if unresolved |
|---|---|---|
| Technical fit | Current process specifications matched to product requirements | Redesign, product-performance shortfall, or a process that cannot support required features |
| Design readiness | PDK and rule status, supported EDA tools and flows, extraction and signoff expectations | Engineering rework and uncertain port schedule |
| IP readiness | Block-level availability, qualification or assessment evidence, licensing, and integration ownership | Replacement or revalidation work and schedule dependency |
| Qualification and quality | Product-specific requirements, reliability evidence, acceptance criteria, failure analysis, and change control | Unplanned qualification work or inability to demonstrate product suitability |
| Economics and schedule | Porting and verification estimate, masks and prototypes, ramp assumptions, capacity, and time to volume | Total cost or time to production that is materially worse than the initial quote suggests |
| Supply and operations | Capacity commitments, logistics, traceability, data access, and engineering response arrangements | Supply interruption or delayed diagnosis of production issues |
| Legal and commercial | Contract terms, IP rights, confidentiality, data handling, export controls, and jurisdiction-specific obligations | Restrictions, compliance exposure, or disputes over data and responsibilities |
Legal and export-control obligations depend on the product, parties, and jurisdictions. Resolve them with the relevant legal and compliance teams rather than assuming that a technical port decision settles them.
Set a go/no-go gate before committing
Move forward only when the team can support a product-specific case: the process fits, design and IP work are understood, qualification evidence and responsibilities are defined, and the total cost and schedule—including ramp risk—are acceptable. If a critical input is still unknown, make it an explicit decision gate with an owner and a date, rather than burying it in an optimistic wafer-price comparison.
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Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
