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Cerebras’ Wafer-Scale Engine (WSE) is an AI processor made from an entire silicon wafer rather than a small die cut from one. Its many compute cores, on-chip SRAM and communication fabric are designed to keep AI calculations and the data they need close together. That differs from conventional GPU systems, which use packaged GPU chips and may spread a large model across multiple processors.
The distinction is architectural, not a guarantee that one system is faster or cheaper for every job. WSE-3 is the processor in Cerebras’ CS-3 system; WSE-3 Turbo (WSE-3T) powers the company’s CS-4 rack-scale system. The chip and the complete computer built around it are not interchangeable terms.
What “wafer-scale” means
Processors are typically fabricated across a silicon wafer, then the wafer is cut into separate dies that are packaged as individual chips. Cerebras instead retains a processed wafer as one large processor. Sandia’s explanation of the approach describes the WSE-3 as integrating 900,000 processors close to high-performance SRAM on the wafer. Sandia deployment announcement
Keeping compute, memory and communication fabric together is intended to reduce data movement. That matters because AI workloads can spend substantial effort moving model data and coordinating work among processors, not just performing calculations. It does not eliminate all communication or guarantee a performance advantage: the workload and software have to make effective use of the design.
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WSE chip versus Cerebras system
WSE names the processor; CS-3 and CS-4 name complete systems. A system includes the hardware and infrastructure needed to operate the processor, rather than being another name for the chip. Cerebras announced WSE-3 for the CS-3 in March 2024, and its current chip page describes WSE-3 Turbo (WSE-3T) as powering CS-4. Cerebras’ WSE-3 announcement · Cerebras’ chip page
How WSE-3 differs from a GPU
A conventional GPU is a packaged processor built from a die cut from a wafer. Large AI jobs may be divided among multiple GPUs, with the system coordinating data and computation across them. WSE-3 instead places a very large compute array, SRAM and communication fabric on a single wafer-scale processor. The table summarizes figures Cerebras published in its 2024 registration statement; they are company-reported comparisons with NVIDIA H100, not universal figures for all GPUs. Cerebras’ registration statement
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| Comparison | Cerebras WSE-3 | NVIDIA H100 |
|---|---|---|
| Processor area | 46,225 mm² | 814 mm² |
| Memory listed in the comparison | 44 GB on-chip SRAM | 0.05 GB on-chip memory |
| Memory bandwidth listed in the comparison | 21 PB/s | 0.003 PB/s |
Cerebras characterizes these figures as 57 times the chip area, 880 times the on-chip memory and 7,000 times the memory bandwidth of H100. These are vendor comparisons, and the company’s filing uses specific terms and measurement scopes; the figures should not be treated as a like-for-like measure of total usable memory or as a direct prediction of application speed. H100 systems also use off-chip high-bandwidth memory (HBM), while WSE-3’s listed SRAM is on the processor.
WSE-3 specifications and what they say
Cerebras’ March 2024 announcement lists these WSE-3 specifications: 4 trillion transistors, 900,000 AI-optimized compute cores, 125 petaflops peak AI performance, 44 GB on-chip SRAM and a 5 nm process. These are manufacturer specifications, not independently verified results for a particular application. Cerebras’ WSE-3 announcement
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Peak performance and core counts describe hardware capacity, not the time a user will see for a specific model. Actual results depend on such factors as model architecture, precision, batch size, software and system configuration. For that reason, headline processor specifications alone cannot establish which system will perform better for a particular workload.
How Cerebras addresses wafer-scale manufacturing
A wafer-sized processor makes manufacturing defects an important design challenge: a flaw cannot simply be avoided by discarding one small die while keeping the rest of the wafer as a conventional chip. Cerebras says the WSE design includes redundant compute cores and routing, and uses a fail-in-place approach that disables flaws and routes around them. This is the company’s description of its manufacturing strategy, not an independent assessment of defect rates or manufacturing yield. Cerebras’ chip page
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How models and systems use the architecture
Keeping work on one processor
Cerebras says a WSE can keep a model on one processor, avoiding the need to split that model across multiple GPUs. The practical benefit depends on whether the model fits the system’s capabilities and whether its software is supported. Cerebras’ developer documentation describes supported models and cluster use; it should be consulted for the specific model and software path under consideration. Cerebras developer documentation
Scaling across multiple WSE systems
For multi-WSE training, Cerebras describes a data-parallel approach: systems work on separate training data rather than dividing one model across WSE processors. That is a different scaling strategy from model partitioning across multiple GPUs, but it does not mean communication disappears or that every training job can use the same approach efficiently. The right comparison depends on how the target workload is parallelized.
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Training, inference and research
Cerebras introduced WSE-3 for AI model training and uses it in CS-3 systems. Sandia announced a CS-3 cluster for research on large AI models, including potential modeling and simulation work. Those deployments illustrate intended and investigated uses; they do not establish that every scientific or AI workload will benefit.
Cerebras also offers inference through an API compatible with the OpenAI Chat Completions API, according to its August 2024 service announcement. Its service availability, supported models and pricing can change, so check the provider’s current service information before relying on them. Cerebras’ inference launch announcement
In a more recent account, Cerebras describes an AWS disaggregated inference setup in which Trainium handles prefill and CS-3 handles decode, with the components connected through AWS networking and offered through Amazon Bedrock. This is Cerebras’ account of that deployment architecture, rather than a general description of all Cerebras inference systems. Cerebras’ account of disaggregated inference
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to evaluate performance claims
In its August 2024 inference announcement, Cerebras reported 1,800 tokens per second for Llama 3.1 8B and 450 tokens per second for Llama 3.1 70B, and described performance as 20 times faster than NVIDIA GPU-based solutions in hyperscale clouds. The announcement also quoted Artificial Analysis reporting above 1,800 output tokens per second for the 8B model and above 446 for the 70B model in its benchmarks. These are dated results tied to specific models and benchmark conditions, not current service guarantees or evidence for other models and configurations. The benchmark statement is quoted by Cerebras; the announcement is not an independent matched comparison across all GPU systems. Cerebras’ inference launch announcement
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteNo universal winner follows from the architecture or these figures. A useful comparison should match the actual model, precision, batch size, software versions, system configuration and measurement method. For a buying or deployment decision, also check model and framework support, system availability, power and facility requirements, and total cost for the intended workload. Cerebras’ developer documentation provides model-support details; the vendor’s comparisons and announcements should be read as company claims unless a separate, comparable benchmark supports them.
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