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Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →A custom ASIC or SoC becomes economically viable when the discounted value of its lifetime savings and other measurable benefits exceeds its added development, production, qualification, and schedule costs. There is no universal break-even volume: the answer depends on the design, the alternative, the product’s life and ramp, and who captures the savings. A quick screen is break-even units ≈ incremental fixed cost ÷ net savings per unit; a real decision needs a lifecycle cash-flow comparison.
Start with technical fit, then calculate the crossover
First establish that each option can meet the product’s performance, power, interfaces, memory, package, and qualification requirements. A platform that cannot meet a must-have requirement is not a meaningful economic alternative. This is especially important for structured ASICs, where available gates, memory, IP, package choices, and performance constrain what can be built. EDN’s comparison of structured and standard-cell ASICs treats technical feasibility as a prerequisite to its cost comparison.
For an initial screen, divide the custom option’s incremental fixed cost by its net saving per shipped unit. If custom development adds $600,000 in fixed cost and saves $15 per unit against the feasible alternative, the arithmetic crossover is 40,000 units. That is a screening calculation, not a forecast: it assumes the full savings apply to every unit, ignores when cash flows occur, and does not account for uncertainty or schedule.
For the decision, compare discounted lifecycle costs for each technically credible route. The established board design is the baseline only if it is what the company would actually keep building. Include components, board and assembly, test, and system-level consequences in that baseline; compare them with the custom route’s NRE and recurring silicon, package, test, and qualification costs. Keep power, performance, footprint, or integration benefits separate unless they are measured and monetized. Otherwise, a presumed chip-cost saving can accidentally count the same benefit twice. EDN’s cost-model discussion recommends an NPV comparison using projected volume, product life, NRE, unit cost, and a discount rate.
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- Air Cooling & Low Noise Operation – This air-cooled ASIC development board runs at 50dB, maintaining stable temperature during long testing sessions.
- 4x BM1370 Chips – Equipped with 4 dedicated BM1370 ASIC chips to deliver steady processing capacity, ideal for chip testing, algorithm verification and embedded system debugging.
- Open Source Firmware – Fully open-source firmware with public code access. Ethernet supports remote monitoring and setting adjustment through a web browser.
- Compact & Lightweight Design – Net weight only 0.45kg, with 10×14×18cm dimensions, perfect for placement on lab benches and workstations.
- Built-in IPS Display – Integrated IPS screen shows real-time operating data for convenient setup and daily testing.
Build a lifecycle model that reflects the actual project
Make a separate model for each feasible route: the existing discrete or board-level design, FPGA or other programmable logic, a structured ASIC if suitable, and a standard-cell ASIC. Use incremental costs: if architecture or RTL work is required for both ASIC choices, for example, it should not be charged to one route as though it were unique. EDN’s case-study method explicitly excludes costs common to its ASIC options.
Fixed costs and one-time work
- Architecture, RTL, verification, and design engineering
- Third-party IP and EDA or tooling costs
- Physical design, masks, and tape-out
- Prototype builds, production-test development, productization, and qualification
- Expected redesign or respin expense and the cost of managing a transition
Recurring cost per shipped unit
- FPGA or ASIC purchase price, including die-area effects where relevant
- Package, production test, and IP royalties
- Board assembly and other system-level costs that change with the design
- Yield-sensitive costs, using project-specific estimates rather than assuming perfect yield
ICsense identifies silicon area, packaging, and testing as major custom-ASIC unit-price drivers; its supplier discussion gives a broad $0.10-to-several-dollars-per-chip range, not a quote for a particular design. Actual price depends on application, technology, die size, package, testing, and volume.
Timing, product life, and benefits
Model annual demand and the ramp, not just total lifetime units. Record when engineering spend occurs, when production can begin, how long the product is expected to sell, and whether a transition delays revenue or causes lost sales. Discount cash flows at a rate appropriate to the company’s decision. Then test conservative, expected, and upside volume, along with delayed production, higher NRE, lower per-unit savings, and a redesign scenario. When the inputs are uncertain, present the break-even as a range or sensitivity rather than a precise point estimate. EDN also flags implementation schedule and lost-opportunity costs as part of the comparison.
Rank #2
- The Coral Dev Board Mini is a single-board computer that enables you to quickly prototype and deploy an embedded system with on-device ML inferencing.
- The board includes the Edge TPU coprocessor, which is a small ASIC designed by Google that accelerates TensorFlow Lite models in a power efficient manner. It's capable of performing 4 trillion operations (tera-operations) per second (tops), using 0.5 watts for each tops (2 tops per watt).
- Provides a complete system: a single-board computer with SoC + ML + wireless connectivity, all on the board running a derivative of Debian Linux we call Mendel, so you can run your favorite Linux tools with this board.
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- Supports AutoML Vision Edge: easily build and deploy fast, high-accuracy custom image classification models to your device..MediaTek 8167s SoC (Quad-core Arm Cortex-A35).2 GB LPDDR3 and 8 GB eMMC memory
Power, performance, size, integration, product differentiation, flexibility, and supply constraints may matter even if they do not reduce the component bill. Assign a value only where there is a defensible business case—for example, a quantified system-cost reduction or revenue effect. Do not treat every custom chip as inherently faster, lower-power, or more reliable. Finally, identify whose economics are being measured: an OEM may capture board and supplier-margin savings, while a semiconductor vendor may calculate its return from chip sales. ARM notes that the same product can therefore have different break-even economics for different participants. ARM’s 2015 white paper also notes that detailed break-even data is often proprietary and varies with complexity, market segment, and volume.
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How the implementation choices differ economically
| Route | Typical economic attraction | Important constraint |
|---|---|---|
| Existing discrete or board-level design | Avoids custom-silicon NRE and retains established components. | May preserve higher component, board, assembly, or system costs; use the real current design as the baseline. |
| FPGA or programmable logic | Flexibility and simpler design changes can be valuable at lower volume or while requirements are unsettled. | Per-unit costs may remain higher. A later FPGA-to-ASIC transition adds redesign work and schedule risk. A historical SEC-filed Form 10-K describes the flexibility and development-cycle trade-off. |
| Structured ASIC | Can offer a middle ground, with lower NRE or implementation time than a standard-cell ASIC when the platform fits. | Available resources and performance constrain fit; unit cost may be higher than a standard-cell ASIC. EDN’s case study illustrates the trade-offs under its stated assumptions. |
| Standard-cell ASIC | Custom implementation may lower die area and recurring unit cost at sufficient volume. | Higher NRE and a longer implementation schedule require a lifecycle comparison, not a chip-price comparison alone. |
Compare only routes that can meet the product’s requirements. A low quoted chip price does not establish the lowest total cost: engineering, package, test, qualification, timing, and the value of flexibility can change the result.
What published break-even figures can—and cannot—tell you
Published numbers are useful as examples of how assumptions affect the answer, not as present-day quotes or universal thresholds.
The “Rule of 50” is an illustration, not a rule for every product
In ARM’s 2015 white paper, Donnacha O’Riordan, then Director of Services Strategy for S3 Group, gave this practitioner example: “If you have a product where $50 in BOM costs can be saved by integrating components off the board, and if you are shipping 50k units of that product per year, then we can justify a custom ASIC.” At those stated figures, the gross BOM saving is $2.5 million per year. The paper describes roughly $2.5 million as a basic working NRE estimate for the example; that estimate covers work from a blank sheet through a tested, packaged IC for prototype-board construction. It is not a current project quote, and gross BOM savings are not the same as net discounted savings after other costs. The same paper’s 12–18-month ROI crossover is a historical typical figure for its discussed board-to-custom-ASIC context, not a schedule promise.
Older EDN examples show why volume alone misleads
An EDN case study published approximately in 2005 modeled a 250,000-gate design at 200 MHz with a 250-pin BGA and a three-to-five-year ASIC life. Its illustrative annual-volume bands favored an FPGA below 1,500 parts, a structured ASIC above 2,000 and below 8,500, and a standard-cell ASIC above 8,500. The accompanying example costs were:
| Option | Reported NRE | Reported unit cost |
|---|---|---|
| FPGA | $0 | $80 |
| Structured ASIC | $200,000 | $40 |
| Standard-cell ASIC | $800,000 | $12 |
These are approximately 2005 study assumptions, not current prices or recommendations. In a separate complex-design example, EDN found a standard-cell ASIC to be the lowest-cost choice at 2,200 units per year for a five-million-gate design with 3-Mbit internal memory and high-speed SERDES. The result underscores that design complexity and unit savings can shift the crossover; it does not establish 2,200 units as a general threshold.
Rank #4
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- ESP32-WROOM-32E Module Inside Built with the ESP32-WROOM-32E wireless module, supporting 2.4 GHz Wi-Fi, Bluetooth and BLE. It is also a programmable ESP32 development board for IoT, smart home, sensor display, dashboard and DIY electronics projects.
- 2.8 Inch 240x320 Touch Display Features a 2.8-inch 240 x 320 TFT LCD touch screen with resistive touch control. Suitable for status display, menu control, graphical interface, monitoring dashboard and custom touchscreen applications.
- Reprogrammable Development Board NerdMiner V2 is only the preloaded application. Users can erase or replace it with compatible ESP32 programs using Arduino IDE, PlatformIO, ESP-IDF or MicroPython for custom development projects.
- Complete Desktop Kit Includes the ESP32-2432S028R-PLUS touch screen development board, 3D-printed protective case and USB Type-C data cable. MicroSD card, battery, touch stylus, sensors and expansion modules are not included.
A title-matched case is still only one case
Electronic Design’s title-matched case article reports a 130-nm ASIC project with flash, analog metals, and thick oxide. The case gives a design-and-mask NRE of $1 million, automotive AEC-Q100 and productization costs of $392,000, an ASIC unit price of $1.46, and a volume of 40,000–45,000 units per month. Those figures belong to that reported project and its period; they should not be treated as current market pricing or as a general break-even point.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What to request before committing to custom silicon
No single published annual-volume threshold establishes viability for a current project. Once technical feasibility is established, request scoped, comparable estimates for the actual architecture, process, package, test, qualification, and geography. Ask design, foundry, packaging, and test participants to identify assumptions and exclusions, and model the volume and schedule risks rather than relying on a headline unit price.
- What is the incremental NRE for each feasible route, and which costs are shared?
- What are the recurring unit costs at the expected volume and ramp, including package and test?
- What qualification, productization, and schedule assumptions are included?
- How does the result change with lower volume, a delayed ramp, a longer or shorter product life, or a redesign?
- Which system-level savings or performance benefits are measurable, and which company captures them?
The useful output is not simply “ASIC” or “FPGA,” but a technically feasible option with an auditable lifecycle cost, explicit assumptions, and a crossover range robust enough for the project’s uncertainty.
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