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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsRapidus and Siemens announced a collaboration to develop design tools and manufacturing flows for Rapidus’s 2-nm process. Siemens is contributing electronic design automation (EDA) technology, including work on a Calibre-based process design kit (PDK) and a reference flow; Rapidus remains responsible for developing and operating its foundry. Rapidus continues to target mass production in 2027, with its April 2026 update specifying the second half of fiscal year 2027. That is a company target—not proof that commercial production, competitive yields, or customer orders are assured.
What the Rapidus–Siemens alliance covers
Announced on June 23, 2025, the collaboration focuses on semiconductor design and manufacturing processes for Rapidus’s 2-nm generation. Its purpose is to connect design work more closely with the process technology Rapidus is developing for its foundry.
Calibre-based process design kit
The companies said they would jointly develop a PDK based on Siemens’s Calibre platform. A PDK gives chip designers process-specific information and rules needed to design and check layouts for a particular manufacturing process. The announcement describes Calibre as supporting physical verification, manufacturing optimization, and reliability assessment from design through fabrication. It does not mean Siemens is building the fab or making Rapidus’s chips.
Reference flow from design through manufacturing
The planned reference flow is intended to cover design, verification, and manufacturing from front end to back end, supporting Rapidus’s Rapid and Unified Manufacturing Service (RUMS). Rapidus’s announcement names Siemens EDA tools Calibre and Solido as part of that flow. The companies presented reliability, speed, scalability, safety, and shorter design cycles as goals; they did not provide independent results demonstrating those outcomes.
The arrangement reflects Rapidus’s manufacturing-for-design approach: coordinating chip design and process development early so customers can move through design and tape-out more efficiently. CEO Dr. Atsuyoshi Koike said Rapidus would “dramatically shorten the time to tape-out” through manufacturing-for-design for its 2-nm gate-all-around process. That statement describes the company’s ambition, not a measured result.
What progress Rapidus has reported
The alliance is one part of a broader foundry-development effort. The milestones below come from Rapidus announcements and should be read as company-reported progress, not independent confirmation of commercial manufacturing performance.
| Date | Rapidus-reported milestone | What it establishes—and what it does not |
|---|---|---|
| June 23, 2025 | Rapidus and Siemens announced plans for a Calibre-based PDK and a design-to-manufacturing reference flow for the 2-nm generation. | Establishes the planned scope of the EDA collaboration; it does not show commercial readiness or production results. |
| April 1, 2025, reported July 18, 2025 | Rapidus said it completed its first EUV exposure at IIM-1 after EUV equipment delivery in December 2024. | A reported equipment and process milestone, not evidence of volume production. |
| June 2025, reported July 18, 2025 | Rapidus said more than 200 pieces of semiconductor equipment had been connected at IIM-1. | Indicates facility build-out progress; equipment connections alone do not establish manufacturing yield or capacity. |
| July 18, 2025 | Rapidus said it had begun prototyping 2-nm gate-all-around (GAA) transistors and that prototype wafers were beginning to produce electrical-characteristic data. | Shows reported prototype work and characterization activity, not proven commercial process performance. |
| April 11, 2026 | Rapidus said its pilot line began in April 2025, it had verified 2-nm GAA transistor operation on 300-mm wafers, and it had made a pre-release PDK available to early adopters while establishing customer prototyping conditions. | Shows reported process and customer-enablement steps; a pre-release PDK and prototype verification are not the same as a production-qualified process. |
| April 11, 2026 | Rapidus said it had achieved its fiscal-year front-end process goals and would continue improving prototype accuracy and implementing yield measures. | Indicates that process development and yield work were ongoing in the company’s account. |
| April 11, 2026 | Rapidus said its Analysis Center had opened for physical, environmental, chemical, electrical, and reliability analysis. It also said Rapidus Chiplet Solutions had begun full-scale operations and cited a prototype 600-mm-square redistribution-layer interposer panel. | Shows reported expansion into analysis and back-end chiplet and packaging development; it does not establish production-scale packaging output. |
Does the 2027 target mean chips will be in production?
No. Rapidus has stated a production target, not a guaranteed start date or a verified commercial outcome. In July 2025, the company said mass production would begin in 2027. Its April 11, 2026 update continued to target production in 2027, and a related April 2026 announcement specified the second half of fiscal year 2027.
That distinction matters because a pilot line, transistor operation on wafers, a pre-release PDK, and customer prototyping are development milestones. They do not by themselves establish that a process can deliver reliable chips at commercial yields and volumes. The reviewed announcements do not establish production yield, wafer capacity, confirmed 2-nm customer orders, or independent validation of the schedule.
How to interpret the Siemens role
Siemens is participating as an EDA and design-flow partner. Calibre and Solido are software tools named in the planned reference flow; the PDK and flow are intended to help designers verify and prepare designs for Rapidus’s process. Rapidus is the company developing the foundry and its manufacturing technology. Siemens’s involvement should not be read as Siemens operating IIM-1, guaranteeing yields, or independently certifying that Rapidus will meet its target.
Rapidus’s design ecosystem has also continued to develop separately from this agreement. In July 2026, Rapidus announced a distinct collaboration with Cadence on agentic-AI support for advanced SoC design. Rapidus and Cadence described up to 2X faster design turnaround as a target for that separate work; it is not a measured outcome of the Siemens alliance.
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