The best-known public estimate for a TSMC N2 wafer is about $30,000 for a 300 mm wafer. That is an industry-reported customer price, not a TSMC-published universal tariff. Some later reporting suggests increases closer to 10%–20% over 3nm for particular products or contracts. The economically meaningful figure is not the wafer price alone, but the cost per good die after yield, packaging, masks, testing and design expenses.
How much does a TSMC 2nm wafer cost?
Public reporting commonly places a 300 mm TSMC N2 wafer near $30,000. TrendForce described the figure as roughly 50% above an approximately $20,000 3nm wafer, based on industry reporting rather than an official TSMC price list: TrendForce’s August 2025 report. A later report suggested some increases could be only 10%–20%, demonstrating that pricing depends on the customer, product, timing and contract: TrendForce, October 2025.
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TSMC does not disclose a standard N2 wafer selling price in its public filings. Treat $30,000 as a credible reported price point, not as a price every customer pays.
| Process | Reported wafer-price reference | Status |
|---|---|---|
| 5nm | About $15,000 | Market estimate |
| 3nm | About $20,000 | Market estimate |
| 2nm/N2 | About $30,000 | Widely reported estimate, not an official tariff |
| Alternative N2 reports | Roughly 10%–20% above 3nm | Conflicting customer and product-specific reporting |
The older-node references appear in market coverage, including this reported comparison. Node names are process-generation labels, not literal measurements meaning that 2nm is simply half the size of 4nm.
What TSMC has confirmed about N2
TSMC says N2 entered high-volume manufacturing in the fourth quarter of 2025 and was expected to ramp rapidly during 2026. Its public materials describe a first-generation gate-all-around nanosheet transistor process. N2P, an enhanced derivative, is scheduled for volume production in the second half of 2026. TSMC also lists A16, a related HPC process with backside power delivery, for volume production in the second half of 2026. See TSMC’s 2025 annual report and N2 technology page.
According to TSMC technical materials, N2 targets approximately 15% higher speed at the same power, or approximately 30% lower power at the same speed, plus more than 15% chip-density improvement versus the previous 3nm generation, depending on the metric and comparison conditions. These are TSMC’s claimed technology comparisons, not a guarantee for every design: TSMC research materials.
Four different meanings of “wafer cost”
Manufacturing cost
This is TSMC’s internal cost to process a wafer: silicon, chemicals, gases, photoresist, utilities, labor, equipment depreciation, maintenance, metrology, engineering and scrap. TSMC does not publish a node-specific N2 cost ledger.
Wafer selling price
This is what a customer pays TSMC for wafer processing—the figure media reports generally mean. It can vary with volume, allocation, delivery schedule, N2 variant, contract date, bargaining power and launch capacity.
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Fully loaded chip cost
A chip company must add electronic-design automation, intellectual-property licenses, masks, probing, packaging, substrates or interposers, final test, logistics, validation and inventory risk.
Retail product cost
A processor inside a phone, graphics card or server also carries memory, board components, cooling, assembly, distribution, warranty, marketing and retail or platform margins. A $30,000 wafer therefore does not make one $30,000 chip.
Why N2 costs more than 3nm
New transistor architecture
N2 moves from the FinFET architecture used by TSMC’s 3nm family to gate-all-around nanosheet transistors. That requires new design rules, device libraries, process-control methods, manufacturing learning and customer validation. TSMC explains the structure here: nanosheet transistor research.
Capital-intensive equipment
Leading-edge fabs require costly lithography, deposition, etch, inspection and metrology tools. Depreciation is a major part of wafer economics. TSMC has said depreciation would rise sharply during the 2nm ramp and that N2 capacity requires more capital per unit of output than comparable N3 capacity: Q1 2026 earnings transcript.
More process complexity
Tighter tolerances and additional process-control work increase cycle time, material consumption, inspection, engineering support and the risk of rework or scrap. TSMC confirms N2’s nanosheet and interconnect innovations, but does not publish a complete public step-by-step cost breakdown: TSMC advanced-technology platform information.
Yield learning
At a new node, the percentage of dies meeting specifications develops over time. TSMC has described N2 yield as good and expected a fast ramp, but that statement does not establish one yield percentage for every customer design. Die area, SRAM content, layout, defect sensitivity and design maturity all matter.
Capacity scarcity and investment recovery
When leading-edge demand from smartphone, HPC, automotive and IoT customers competes for limited capacity, price reflects scarcity as well as manufacturing cost. TSMC is also recovering fab, cleanroom, utility, equipment and process-development investments. The resulting price is a blend of cost-plus economics, market pricing and strategic margin management.
How many chips fit on a 2nm wafer?
A 300 mm wafer contains many rectangular die positions, not one chip. Edge exclusion, scribe lanes and die geometry reduce the theoretical count. Yield then determines how many positions become usable products.
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Use this basic model:
Cost per good die = wafer price ÷ gross dies per wafer ÷ final wafer yield
A fuller model adds processing and packaging costs:
Cost per good die = (wafer price + processing add-ons) ÷ (gross dies × electrical yield × packaging yield)
Illustrative cost-per-die examples
The following calculations assume a $30,000 wafer and 70% electrical yield. They are illustrations, not TSMC production data.
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Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →| Approximate die size | Illustrative gross dies | Good dies at 70% yield | Wafer-only cost per good die |
|---|---|---|---|
| 100 mm² mobile SoC | About 650 | About 455 | About $66 |
| 200 mm² processor | Roughly half the 100 mm² count | About 225–230 | About $130 |
| 400 mm² accelerator | Roughly one-quarter of the 100 mm² count | About 110–115 | About $260 |
| 600 mm² accelerator | Much lower and more edge-sensitive | Highly design-dependent | Potentially several hundred dollars |
Large dies lose twice: fewer fit on each wafer, and a larger surface area gives defects more opportunity to make a die unusable. Chiplets can divide a large design into smaller dies, improving yield economics, although advanced assembly and interconnect add cost.
Masks, packaging, memory and testing
A mask set is a separate, mostly upfront expense. It provides the lithographic templates used to manufacture a design; the wafer quote pays for processing each wafer. Leading-edge masks are expensive because of complex layers, advanced lithography, inspection and possible tape-out revisions. TSMC discusses mask-related services but does not publish a universal N2 mask price: TSMC filing.
High-performance products may also require advanced packaging, silicon interposers, chiplet assembly, high-bandwidth memory, costly substrates, thermal solutions and final test. For AI accelerators, packaging and HBM supply can be as important as wafer fabrication. TSMC describes its 3DFabric ecosystem and HPC positioning in its annual report and HPC technology materials.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Does a higher wafer price lower cost per transistor?
Not automatically. A useful conceptual measure is:
Cost per transistor = cost per good die ÷ usable transistors per good die
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesN2 density, performance and power gains can offset part of its wafer premium when they enable a smaller die, more compute in the same area or lower system power. However, SRAM, analog, I/O, memory interfaces and power-delivery structures may not scale like logic. The result must be calculated for the specific design.
When is N2 worth the premium?
Reasons to adopt N2
- Higher performance per watt and greater logic density.
- A smaller die or more functionality within the same area.
- Lower power within a fixed thermal envelope.
- Competitive differentiation and earlier access to leading-edge capacity.
- Potentially higher product revenue or longer battery life.
Reasons to stay on N3 or an older node
- Lower wafer, mask and engineering costs.
- More mature yield and established intellectual property.
- Sufficient performance for the product.
- Lower redesign, qualification and schedule risk.
- Better capacity availability or a lower selling price.
The correct test is whether N2 reduces the total cost per useful unit of performance, battery life, compute or revenue enough to justify wafer, mask, design, packaging and schedule costs.
N2, N2P and A16 are not interchangeable
| Technology | Position | Timing stated by TSMC |
|---|---|---|
| N2 | First-generation nanosheet 2nm process | High-volume manufacturing began Q4 2025 |
| N2P | Enhanced N2 derivative | Volume production scheduled for H2 2026 |
| A16 | HPC-focused nanosheet technology with Super Power Rail backside power delivery | Volume production scheduled for H2 2026 |
A report saying “2nm pricing” may refer specifically to N2, an N2P arrangement or a broader family contract. Identify the exact process before comparing prices. TSMC’s timing and positioning are documented in its logic technology page, annual report and HPC platform materials.
Common mistakes when interpreting the $30,000 figure
- Calling it an official list price: it is a reported estimate or customer quote.
- Confusing a wafer with a chip: one wafer contains many die positions.
- Ignoring yield: gross positions are not necessarily good products.
- Using wafer price as finished-chip cost: masks, packaging, memory, testing and design remain.
- Comparing node labels literally: “2nm” is a generation name, not a complete physical measurement.
- Assuming every customer pays the same: volume, timing, allocation and contract terms change pricing.
- Assuming every N3 variant is equivalent: N3, N3E, N3P, N3X and N3C have different economics.
- Assuming geography is irrelevant: fab location can change construction, labor, utilities, logistics and incentives.
The Bottom Line
Bottom line: About $30,000 per 300 mm wafer is a defensible public estimate for TSMC N2, but not a verified universal price. The actual economics depend on contract terms, die size, yield, masks, packaging and testing. N2’s premium can be rational for high-value processors that need its performance, power or density; it is not automatically the best choice for every chip.
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