TSMC’s first Arizona fab began high-volume production of chips using the company’s N4, or 4nm-class, process in the fourth quarter of 2024. TSMC and the U.S. Commerce Department say yields are comparable with Taiwan, so the technical milestone has been achieved. The unresolved issue is economics: Arizona-made chips carry a higher cost, but there is no single, publicly disclosed surcharge that applies to every wafer or customer.
What TSMC actually started in Arizona
The facility is TSMC Arizona’s first fab, generally identified as Fab 21 Phase 1 or Phase 1A in Phoenix. TSMC’s annual report and Arizona site confirm that it entered high-volume N4 production in Q4 2024, rather than merely running pilot or risk-production lots. See TSMC’s 2025 annual report and the TSMC Arizona site.
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N4 is a process-generation name, not a literal measurement describing every transistor feature. “4nm-class” is therefore the clearest shorthand for the technology. TSMC’s earnings-call transcript says the Arizona fab reached high-volume N4 production with yield comparable to its Taiwan fabs: Q4 2024 transcript.
High-volume manufacturing means the fab is producing wafers at commercial scale. It does not, by itself, prove that the site has Taiwan-level throughput, utilization, cycle time, supplier responsiveness or profitability.
“Higher cost” is several different claims
Reports often collapse construction expense, wafer-processing cost and finished-chip pricing into one number. They are not interchangeable.
| Figure | What it measures | How to interpret it |
|---|---|---|
| Four to five times higher | Earlier estimates of U.S. fab-building and facility construction costs versus Taiwan | Applies to capital construction, not to the price of each chip |
| Up to 50% higher | Earlier U.S. government discussion of potential wafer costs | An earlier estimate, not a current universal surcharge |
| About 10% higher | TechInsights’ modeled Arizona wafer-processing cost | An operating-cost estimate, not a TSMC price list |
| More than 5% but less than 20% | AMD CEO Lisa Su’s comparison of chips from TSMC’s U.S. facilities with comparable Taiwan-made chips | A customer-side range attributed to AMD, not all TSMC customers |
| 5%–10% | Industry reports about possible advanced-node price increases | Market reporting that is not confirmed as an Arizona-specific rate |
The U.S. Commerce Department’s cost analysis is available in its Section 9904 report. TechInsights’ approximately 10% estimate was reported by Tom’s Hardware. AMD’s public range was reported by Bloomberg. None establishes a standard Arizona surcharge for every product.
Why Arizona wafers cost more
Construction and depreciation
Building a leading-edge fab in the United States requires expensive cleanrooms, specialized utilities and process infrastructure. Those costs are spread over years of wafer output. A smaller or newly ramping fab consequently carries more depreciation per wafer than a heavily scaled Taiwan megafab.
Scale and utilization
Taiwan has a dense network of fabs, suppliers and experienced production teams. Arizona’s initial output is much smaller than TSMC’s overall Taiwan capacity. Early-ramp utilization can make fixed costs look unusually high; the economics may improve as more tools run continuously and additional fabs share local infrastructure.
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Arizona must recruit and train a workforce for advanced manufacturing while developing local sources for chemicals, gases, spare parts and maintenance. Taiwan’s mature ecosystem can provide many inputs faster and at larger volume.
Logistics and packaging
Wafer fabrication is only one stage of semiconductor production. Packaging, testing, transport and final assembly affect delivered cost. If later steps occur outside Arizona, “made in the United States” may describe fabrication rather than the entire supply chain.
What comparable yield does—and does not—show
Yield is the share of dies on a wafer that meet specifications. TSMC and Commerce Department announcements describe Arizona yields as comparable with, or on par with, comparable Taiwan production. That demonstrates process quality and usable-die performance.
Yield parity does not establish equal throughput, cycle time, reliability at full utilization, logistics cost or margin. A new fab can match yield while still producing fewer wafers and carrying higher depreciation.
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Commercial contracts are private, so there is no public universal Arizona price. TSMC may charge more for U.S.-made capacity, pass through part of its cost, or negotiate different terms by customer and product. Chip designers can absorb some of the difference, while system companies may pass some cost through to buyers of phones, GPUs, servers, vehicles or other electronics.
Lisa Su’s July 2025 estimate—more than 5% and less than 20% above comparable Taiwan-made chips—should be read as AMD’s customer-side observation, not as a promise that every TSMC customer pays that amount. The final premium can also reflect demand, packaging, transport, contractual terms and the strategic value of assured supply.
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Why build in Arizona if Taiwan is cheaper?
The project is not designed solely to minimize wafer cost. It addresses concentration risk and customer requirements.
- U.S. customers can obtain a geographically diversified source of advanced logic.
- Domestic capacity reduces exposure to a potential Taiwan Strait disruption.
- Defense, aerospace, automotive and data-center buyers may value local or allied supply even when it costs more.
- The project supports the goals of the CHIPS and Science Act and the rebuilding of a U.S. semiconductor ecosystem.
- Government support can narrow the gap between U.S. and Taiwan economics.
In November 2024, the Commerce Department finalized up to $6.6 billion in direct CHIPS funding for TSMC’s project, alongside potential loans and tax incentives: Commerce Department announcement.
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TSMC’s original plan selected Phoenix in 2020. In December 2022, it announced N4 production for the first fab and a planned second fab for 3nm-class technology: TSMC announcement. The company’s Arizona materials now describe a broader multi-fab and advanced-packaging program, while its expanded U.S. investment plan has been described as reaching $165 billion: TSMC’s expansion release.
How much capacity is available?
Early reports described roughly 10,000 wafer starts per month during the initial ramp. That is a ramp-stage estimate, not a guaranteed permanent rate. It should not be confused with the eventual capacity of Phase 1, a second fab, the full Arizona cluster or TSMC’s much larger N4/N5 capacity in Taiwan. See the capacity discussion in Tom’s Hardware.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Which products are made there?
Arizona N4 capacity is intended for advanced chips used in areas such as smartphones, high-performance computing, artificial intelligence and other applications. TSMC and U.S. government descriptions mention smartphones, autonomous vehicles and AI data-center servers, but they do not provide a complete customer-product-fab map: Commerce bulletin.
Do not assume that a particular Apple, Nvidia or AMD product is Arizona-made unless the customer or TSMC explicitly confirms it. The same process generation can be used in several fabs, and product-level manufacturing locations are often confidential.
How to judge whether the project succeeds
- Technical parity: Arizona must sustain Taiwan-comparable yield and reliability.
- Utilization: Wafer starts must rise enough to dilute fixed costs.
- Customer acceptance: Buyers must continue paying, or sharing, the U.S. premium.
- Public support: Grants, tax credits and other incentives must justify their cost.
- Ecosystem depth: Local materials, packaging and testing should reduce logistics dependence.
- Financial returns: Successful operation is not the same as project profitability.
- Expansion economics: New fabs should improve scale rather than multiply underused capacity.
Industry reporting has also discussed possible 5%–10% advanced-node price increases, but that reporting is not a confirmed Arizona-specific tariff: Taiwan News.
What the milestone means for U.S. semiconductor policy
Arizona should not be judged only by whether it matches Taiwan’s lowest manufacturing cost. It creates domestic advanced-logic capability, reduces geographic concentration and helps build a workforce and supplier base. Those benefits have strategic and economic value, but they do not eliminate the need to test utilization, customer pricing and returns on public incentives.
The central trade-off is straightforward: Taiwan remains TSMC’s scale and cost benchmark, while Arizona offers diversification and supply assurance at a premium. Construction can be several times more expensive without making each finished chip several times more expensive; wafer cost, customer price and delivered product cost must be kept separate.
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