TSMC’s second quarter of 2024 showed why the world’s leading contract chipmaker could consider charging more: artificial-intelligence and high-performance-computing demand filled advanced wafer and packaging capacity faster than it could be expanded. TSMC officially reported a strong quarter and raised its outlook; reports that it was considering price increases of roughly 5% to 10% for some advanced-node products, and potentially larger cumulative increases for CoWoS packaging, were not a published company-wide price list.
How strong was TSMC’s Q2 2024?
Reported on July 18, 2024, TSMC’s results showed substantial sequential growth and a 53.2% gross margin. Taiwan-dollar and U.S.-dollar growth rates differ because currency translation affects the comparison.
| Measure | Q2 2024 result | Comparison or qualification |
|---|---|---|
| Revenue | NT$673.51 billion | Up 13.6% sequentially in Taiwan dollars; up 10.3% in U.S. dollars |
| Net income | NT$247.85 billion | Up 9.9% sequentially |
| Diluted EPS | NT$9.56 | Equivalent to US$1.48 per ADR unit |
| Gross margin | 53.2% | Company-reported quarterly margin |
| Q3 2024 revenue guidance | US$22.4 billion–US$23.2 billion | About 9.5% sequential growth and approximately 32% year-over-year growth at the midpoint |
TSMC also lifted its 2024 revenue-growth expectation to slightly above the mid-20% range in U.S. dollars, compared with its earlier low-to-mid-20% outlook. The official figures and guidance are in TSMC’s Q2 earnings materials and its SEC-filed earnings release.
AI and advanced processes powered the quarter
High-performance computing became the largest application
High-performance computing (HPC), including AI-related chips, became TSMC’s largest application category and exceeded half of revenue in contemporaneous coverage. AI accelerators require both advanced logic manufacturing and sophisticated packaging, so demand affects more than the front-end wafer fab.
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TSMC does not disclose revenue by individual customer in the earnings release. The evidence supports strong HPC and AI demand as a central driver, not a claim that one named customer alone produced the quarter’s growth. Smartphone seasonality remained a partial offset, demonstrating that not every end market was recovering equally.
Most wafer revenue came from newer process generations
In Q2, 3nm supplied 15% of wafer revenue, 5nm supplied 35%, and 7nm supplied 17%. Together, 7nm-class and newer technologies represented 67% of wafer revenue. These labels identify process generations and commercial technology families; they are not literal measurements of every transistor dimension.
Why a strong quarter can lead to higher prices
Scarce capacity has a higher value
When AI customers need additional leading-edge wafers or advanced packaging, guaranteed capacity becomes strategically valuable. A customer may accept a higher quote to protect a product launch rather than risk an unavailable alternative.
Expansion is unusually capital-intensive
TSMC is funding new process generations, additional fabs, advanced packaging, and manufacturing sites outside Taiwan. Its 2024 annual report describes the technology and capacity investments behind that expansion. Higher prices can help earn an adequate return while construction, equipment, energy, labor, and depreciation costs rise.
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A newer node also costs more to operate because of process complexity, masks, design rules, equipment, and yield learning. It is not simply an older wafer with a higher markup.
Customers cannot switch immediately
Large fabless designers generally need new process-design kits, layout or mask changes, yield qualification, packaging work, software validation, and product testing to move a design. Samsung Foundry and Intel Foundry, older TSMC nodes, and chiplet architectures can be alternatives for particular products, but substitution is not an instant remedy for a high-volume leading-edge program.
What price increases were reportedly under consideration?
Industry reports in July 2024 pointed to possible increases of approximately 5% to 10% for selected advanced-node manufacturing, particularly 5nm-, 4nm-, and 3nm-class products. Reports also suggested that CoWoS and other advanced-packaging services could see cumulative increases of roughly 10% to 20% over a longer period. Tom’s Hardware summarized analyst and industry expectations in its pricing report; Golem provided additional reported ranges in its July coverage.
Those figures were reports, not an official TSMC tariff. The eventual amount could vary by node, product, order volume, customer, contract, and timing. An increase might apply only to incremental capacity while existing contracted volume remained under earlier terms. Exact customer-by-customer changes were not publicly confirmed.
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Why CoWoS is as important as wafer capacity
CoWoS (Chip on Wafer on Substrate) is an advanced packaging technology that combines logic dies with high-bandwidth memory and other components in a high-performance package. AI accelerators can be limited by packaging throughput even when enough front-end wafers are available. That means the supply bottleneck for a complete accelerator system may occur after wafer fabrication.
TSMC’s 2024 annual report and Q2 materials discuss advanced packaging and capacity strategy, but they do not establish one clean official Q2 CoWoS-capacity number. The commercially relevant point is that constrained packaging can support higher negotiated prices alongside constrained leading-edge wafers.
Which companies could feel the effect?
Potentially exposed designers include Nvidia, AMD, Apple, Qualcomm, MediaTek, and Broadcom, all of which use TSMC manufacturing or could use affected advanced nodes or packaging. Exposure is not uniform: each company’s node mix, packaging requirements, order volume, contract terms, and ability to absorb costs differ. No public evidence establishes that every named company received the same increase.
How a TSMC increase travels through the supply chain
- TSMC manufacturing price: The foundry charges more for a wafer, package, or incremental capacity.
- Customer chip economics: The designer absorbs the cost, negotiates with TSMC, redesigns part of the product, or raises its own chip price.
- System cost: Board, server, graphics-card, smartphone, or PC makers evaluate the resulting bill-of-materials change.
- Retail outcome: The final price may rise, stay unchanged, or be offset by lower margins and other component costs.
A 5% to 10% wafer-price increase therefore does not translate into a 5% to 10% increase in a finished phone, graphics card, server, or PC. The wafer’s share of the product cost, customer contracts, competition, and pricing strategy determine the pass-through.
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Could customers move to Samsung or Intel Foundry?
They can consider Samsung Foundry, Intel Foundry, mature TSMC nodes, chiplet designs, or co-developed manufacturing arrangements. The trade-off is time and execution risk. A move can require porting layouts, new masks and design rules, yield qualification, packaging changes, software validation, and a new production ramp. For a product tied to an AI launch or a high-volume shipment schedule, those costs may outweigh a near-term wafer-price increase.
That does not mean TSMC has no competition. Alternative foundries may be credible for selected nodes, products, or customers, and sustained price pressure could encourage diversification over time.
What the pricing story means for TSMC investors
Potential benefits
- Selective increases can monetize scarce leading-edge and packaging capacity.
- Higher prices can help fund new nodes, overseas fabs, and expanded CoWoS capability.
- Strong AI/HPC demand can support revenue even while smartphone demand is seasonal.
Risks and limits
- AI infrastructure spending could slow, reducing urgency for extra capacity.
- Customers may redesign products, adopt chiplets, or qualify competing foundries.
- Higher prices could weaken demand in price-sensitive consumer segments.
- New overseas fabs may dilute margins during construction and ramp-up.
- Revenue can rise without margin expansion if construction, energy, labor, and depreciation costs rise faster.
- Automotive, smartphone, and other mature-node markets may remain soft enough to offset part of AI strength.
Indicators to monitor
- Gross-margin direction as new fabs and packaging lines ramp.
- 3nm utilization and the timing of 2nm production.
- CoWoS expansion and evidence of continuing packaging tightness.
- Q3 results and the full-year growth outlook.
- Recovery in smartphones and automotive chips.
- Customer adoption of Samsung, Intel, mature-node, or chiplet alternatives.
Bottom line
TSMC’s Q2 2024 proved that AI and HPC demand was converting into real revenue and profit: NT$673.51 billion of revenue, NT$247.85 billion of net income, and stronger guidance. That success also exposed a supply constraint spanning advanced wafers and CoWoS packaging. Reported price increases were best understood as selective, negotiated pricing power used to manage scarcity and fund expansion—not as a confirmed universal 10% surcharge. Customers may absorb some of the cost, pass some through, or invest in alternatives, so higher TSMC prices do not automatically mean proportionally higher consumer prices.
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