CoreLab says its reusable, open-architecture platform could reduce the entry cost of developing a custom AI processor by 75% or more. The company’s founder, Allen Wu, told EE Times on March 5, 2026, that traditional high-performance custom-compute IP budgets have exceeded $100 million. That is a reported benchmark and a cost-reduction target—not proof that a customer can now build and ship a production AI chip for a specified price.
How CoreLab says it could lower the entry cost
The proposal is to start with reusable processor IP and design infrastructure, then customize the platform for a particular workload instead of building every part of a compute stack from scratch. CoreLab describes its intended role as something like a shared platform for compute: common infrastructure that customers can adapt, rather than a single fixed processor design.
That approach could reduce duplicated development and make it easier to combine processor and accelerator elements. It does not mean that all customer-specific engineering disappears, or that every chip built on the platform will have the same cost. CoreLab has not published a price list or an independently verified cost breakdown showing how the stated reduction would be achieved in a production program.
| Figure | What it describes | What it does not establish |
|---|---|---|
| More than $100 million | Traditional high-performance custom-compute IP budgets, as CoreLab founder Allen Wu described them to EE Times in 2026. | A universal industry minimum, a complete chip-program budget, or the amount every prospective customer must spend. |
| 75% or greater reduction | CoreLab’s stated target for reducing the entry cost of custom AI-chip development, as reported by EE Times in 2026. | A price quote, a realized saving, or independently verified production results. |
The distinction matters for a startup evaluating a custom chip. CoreLab’s claim concerns the cost of getting into custom development relative to the traditional barrier described by Wu. The available information does not specify whether the target covers every engineering and production expense a customer might incur, nor does it show what a particular design would cost.
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What kind of processor is CoreLab proposing?
CoreLab’s architecture is intended to support a mix of compute elements rather than prescribe one processor type for every task. Wu told EE Times that a future AI processor could combine a CPU, a CUDA-type GPU core and a domain-specific accelerator (DSA), and described the result as a custom fusion processor, or XPU.
RISC-V is a baseline, not an exclusivity rule
RISC-V is part of CoreLab’s baseline and interoperability strategy; the proposal is not to exclude Arm or other architectures. CoreLab says its platform is open to multiple processor architectures so designers can combine or customize components for their intended product. That flexibility is a design objective, not evidence that every architecture or software toolchain is already supported in every configuration.
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Why physical AI is a target
CoreLab emphasizes robotics and autonomous systems, where physical-AI workloads can involve changing combinations of perception, language and action. It argues that a reusable, adaptable platform could help hardware evolve as software approaches such as vision-language-action systems and world models develop. The materials available do not provide benchmarks showing how CoreLab-based systems perform on those workloads.
What is the Atlantis platform?
Atlantis is a CoreLab–Tenstorrent collaboration announced on September 25, 2025, for robotics and automotive edge applications. Tenstorrent contributes RISC-V CPU IP; CoreLab contributes energy-efficient IP and system-on-chip (SoC) solutions. The companies describe deep customization, low total cost of ownership and safety-ready CPU IP as design goals.
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Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →EE Times reported that the first concrete implementation is built around eight Tenstorrent high-performance cores, with CoreLab RISC-V real-time security and power-management IP. It also reported an open PCIe slot for accelerator cards, giving engineers a way to experiment with add-on accelerators before committing to a full SoC.
Is Atlantis a Tenstorrent chip?
It is more accurate to call Atlantis a joint platform than to attribute the whole product to one company. The reported CPU cores are Tenstorrent IP, while CoreLab supplies other IP and SoC solutions. The announced partnership is specifically aimed at customizable robotics and automotive edge designs.
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When will the development board be available?
EE Times reported that Atlantis development boards were planned for Q4 2026. That is a reported development target, not confirmation that boards are currently on sale or that a retail product has launched. The available information does not establish an Atlantis Amazon listing or product SKU.
Can a startup build a custom AI processor for less than $100 million?
CoreLab’s stated goal is to lower the entry cost, but the information available does not verify a specific sub-$100-million customer budget. Wu’s more-than-$100-million figure concerns traditional high-performance custom-compute IP budgets as described in the EE Times interview; it should not be read as a universal minimum for every chip or as a complete accounting of all costs in a chip program.
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For a prospective buyer, the useful next step is to ask what the quoted scope includes. A platform or IP license, a turnkey design engagement and a finished production chip are not interchangeable deliverables. CoreLab has not disclosed pricing, customer deployment data, tape-out status or independently audited benchmarks that would allow a buyer to confirm the claimed savings or compare total program costs.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Does CoreLab sell RISC-V IP or turnkey chip design?
CoreLab describes a range of services rather than a single purchase model. EE Times reports that customers may license IP outright or buy a full turnkey solution. CoreLab’s website lists processor customization, end-to-end design and integration/testing, technical support, flexible licensing, RISC-V core IP, system solutions and design services.
That gives potential customers more than one way to engage: license components for an internal design effort, or seek broader design and integration support. The company has not published prices or enough detail to determine which route would be less expensive for a given customer.
What a buyer should verify before committing
A lower entry-cost target is only one part of a chip decision. A startup considering CoreLab or any custom-compute platform should establish the project scope and evidence behind the offer before treating the target as a budget.
Quick Recap
- Cost scope: Ask which IP, engineering, integration and support work is included in a quote, and what remains the customer’s responsibility.
- Architecture and tools: Confirm which processor configurations, accelerators and software toolchains are supported for the intended workload.
- Expansion and customization: Determine whether the PCIe accelerator route and the desired SoC-level customization fit the planned product.
- Security and safety: Request details on the relevant IP and evidence for any safety or security requirements in the target application.
- Schedule and maturity: Clarify what is available now, what is still in development and what milestones stand between a development board and a production design.
- Performance evidence: Request workload-specific results and the conditions under which they were measured; the information reported so far does not provide independently audited benchmarks.
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