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NXP announced the i.MX 95 on January 4, 2023, introducing an applications-processor family that combines 3D graphics and an integrated neural-processing unit with real-time cores, camera and video hardware, and high-speed networking. NXP now lists the family as active. It is aimed at embedded systems such as automotive controllers, industrial machines, vision gateways and connected equipment—not consumer PCs. Its significance is the combination of these capabilities in one platform, rather than a measured performance improvement over a named predecessor.
What NXP announced—and why it mattered
At CES in Las Vegas on January 4, 2023, NXP announced the i.MX 95 as a new family in its i.MX 9 applications-processor series. The launch marked several firsts for NXP’s i.MX applications processors: an Arm Mali GPU, NXP’s eIQ Neutron NPU, a newly highlighted image-signal-processing and vision architecture, a 10GbE interface, and LPDDR5 support. NXP’s launch announcement positioned the family for automotive, industrial, IoT, medical, aerospace and networking applications.
As of August 18, 2026, NXP’s product page lists the family as active. That current product status is distinct from the original 2023 announcement: the launch introduced the processor family, while later product and distributor listings reflect its subsequent commercialization.
How the processor divides its work
The i.MX 95 is a heterogeneous system-on-chip: different processor blocks are intended for different classes of work, rather than every task running on the same cores. NXP lists six Arm Cortex-A55 application cores, one Cortex-M7 real-time core and one Cortex-M33 real-time core, alongside the eIQ Neutron NPU. The product page also specifies 1,376 kB of on-chip SRAM with ECC and support for LPDDR5 or LPDDR4X memory at up to 6.4 GT/s on a 32-bit interface, with inline ECC and encryption.
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- Cortex-A55 cluster: Runs application software, commonly Linux or Android, including user interfaces and higher-level application services.
- Cortex-M7: Supports deterministic real-time workloads and control functions.
- Cortex-M33: Supports lower-power real-time work and safety-management tasks.
- eIQ Neutron NPU: Accelerates compatible neural-network inference, reducing the need to run all supported AI workloads on the application CPUs.
NXP’s ecosystem documentation describes the architecture as combining application computing with real-time and machine-learning resources. The practical appeal is a system that can run a rich interface or vision application while assigning time-sensitive control to a separate real-time domain. That division still requires software integration; it does not mean all cores run the same operating system or that the M-class cores automatically certify the finished product as safe.
What the 3D graphics add
NXP identifies an Arm Mali 3D GPU, a separate 2D GPU, and display interfaces including MIPI-DSI and LVDS. Its current product information lists support for OpenGL ES 3.2, Vulkan 1.2 and OpenCL 3.0. NXP’s ecosystem document identifies the GPU as a Mali G310; the general product page uses the broader Arm Mali description.
These graphics resources are relevant to automotive displays, industrial operator panels, medical interfaces and robotics systems that need more than basic 2D composition. NXP lists display configurations through MIPI-DSI of up to 4Kp30 or 3840×1440p60. API support is not a guarantee of a particular application’s frame rate, rendering resolution or compatibility: results depend on the software stack, memory configuration, thermal limits, drivers and workload. NXP positions the GPU for embedded graphics rather than gaming.
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What the NPU can—and cannot—promise
The eIQ Neutron NPU is intended to accelerate machine-learning inference on the device. That can support tasks such as object or scene recognition, industrial inspection, smart-camera analysis, automotive perception and voice or sensor intelligence without sending every input to a cloud service.
NXP’s ecosystem document names an eIQ Neutron N3-1024S and describes performance of up to 8 TOPS. Treat that as an attributed maximum claim, not a universal measure of application speed: partner modules and boards list lower figures, including 2 TOPS, and the available evidence does not establish that all figures refer to the same silicon configuration or measurement conditions. TOPS is a theoretical throughput measure, not an end-to-end inference benchmark.
Real-world acceleration depends on whether a model’s operators are supported by the compiler and runtime, whether the model needs quantization or conversion, and how much time is spent moving and preparing data. Unsupported operations can fall back to a CPU or another accelerator, affecting speed and power consumption. A useful comparison therefore uses the same model, precision, preprocessing and postprocessing, as well as comparable power and thermal limits.
Vision and video paths
The chip pairs an image signal processor with multiple MIPI-CSI camera interfaces and a 4K video-processing unit. NXP lists camera-path configurations of one 4Kp60 camera, two 4Kp30 cameras, four 1080p60 cameras, or eight 1080p30 cameras using MIPI virtual channels. The display paths include MIPI-DSI and LVDS.
Those figures describe interface and pipeline capabilities, not a promise that every camera can run at its listed maximum alongside every other camera, display, codec and AI workload. A design’s achievable combination depends on memory bandwidth, board routing, software and the rest of the video pipeline.
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The i.MX 95’s connectivity helps explain its fit for gateways, controllers and high-bandwidth edge appliances. NXP lists one 10GbE port and two 1GbE ports, with TSN-related capabilities as well as AVB and IEEE 1588 synchronization features. The family also includes two PCIe Gen 3 x1 interfaces, USB 3.0 Type-C and USB 2.0 Type-C interfaces, five CAN FD interfaces, three SD/SDIO/eMMC interfaces and Octal SPI support for NOR and NAND. Other listed interfaces include UART, I²C, SPI, I3C, FlexIO, ADC, audio, camera and display connections.
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This mix can suit automotive domain or zonal controllers, industrial Ethernet gateways, machine-vision systems and robotics. It is a chip-level inventory: an evaluation board or system-on-module may not route every interface to an accessible connector, and board designs determine which capabilities can be used together.
Safety and security require system-level work
NXP includes the i.MX 95 in its SafeAssure portfolio and describes it as a platform for safety-enabled development. The product page also lists EdgeLock Secure Enclave capabilities, secure boot, secure debug and update, firmware signing and authentication, encryption, and hardware root-of-trust features. Current NXP materials also reference hybrid ML-DSA/ECDSA handling for NXP-signed Secure Enclave firmware; this is a product-page claim whose implementation and support details can evolve.
These features can support a product’s safety and security architecture, but they do not make a customer’s complete product automatically ASIL- or SIL-certified, nor do they make it immune to attack. Certification and security depend on the complete hardware and software design, development process, configuration and applicable assessment.
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Software and development hardware
NXP lists Linux, Android and FreeRTOS support, as well as commercial operating systems including QNX and Green Hills Software. Development teams should evaluate the relevant board-support package, Linux or Yocto integration, GPU-driver maturity and eIQ model-conversion workflow for the exact board and software release they plan to use. The existence of an API or operating-system listing does not establish equal maturity across all releases.
Three common hardware routes have different trade-offs:
| Route | What it offers | Best suited to |
|---|---|---|
| FRDM-i.MX 95 | NXP lists an i.MX 95 with 8 GB LPDDR4X-4000, 32 GB eMMC 5.1, microSD, MIPI-CSI/DSI and LVDS-to-HDMI connectivity. | Initial software and peripheral evaluation where a compact, relatively simple development entry point is useful. |
| IMX95LPD5EVK-19 | A 19×19 mm system-on-module and baseboard; its guide lists 16 GB LPDDR5, 64 GB eMMC, 10GbE and 1GbE, camera and display interfaces, PCIe, USB, CAN and audio. | Broader interface validation, including camera, display, PCIe and Ethernet paths. |
| Partner system-on-module | NXP’s product page lists solutions from multiple partners. Memory, clocks, wireless options, temperature ratings, software support and NPU claims vary by module. | Projects seeking to reduce DDR and carrier-board design work, subject to module-specific constraints and vendor support terms. |
| Bare processor | Maximum flexibility over memory, carrier-board design, thermal management and I/O, with corresponding board-design responsibilities. | Production designs with the expertise and schedule to develop and qualify a custom platform. |
NXP’s FRDM-i.MX 95 page lists the board’s processor and memory configuration. The IMX95LPD5EVK-19 characteristics above are from NXP’s evaluation-kit guide. Board configuration is not the same as the full capabilities of the SoC, so confirm connector exposure, memory and software support against the intended application before choosing a kit.
When the i.MX 95 is a good fit
The family is most compelling when a design genuinely needs several of its capabilities together. Its graphics, AI, vision, real-time processing and networking combination may justify the integration effort in a higher-end embedded product; for a simpler design, the additional complexity can be unnecessary.
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|---|---|---|
| High-end vision gateway | Strong | Combines camera and video hardware, local inference, application processing and high-speed networking. |
| Automotive HMI or controller | Strong, subject to system design | Offers 3D graphics, application cores, real-time domains, CAN FD and safety-oriented platform features. |
| Industrial controller | Strong where workloads warrant it | Can unite operator graphics, deterministic control and Ethernet or TSN-related connectivity. |
| Simple embedded display | Often excessive | A product without demanding 3D, AI or networking requirements may not benefit from the added compute and integration burden. |
| Battery-powered sensor node | Often a poor fit | Six application cores, external high-bandwidth memory and advanced graphics may exceed a modest power budget. |
| Low-cost MCU product | Poor fit | A microcontroller is generally more appropriate when the product needs simple control rather than application-class computing. |
Before committing, assess the model workload against the eIQ toolchain, the required camera and display combination, sustained thermal behavior, operating-system and BSP support, and which interfaces the selected board or module exposes. More integrated capability can mean more software and debugging work, and a module’s convenience comes with vendor, connector and configuration constraints.
Why the i.MX 95 matters
The i.MX 95’s defining feature is not a single GPU, NPU or interface. It is the integration of embedded 3D graphics, neural-network acceleration, vision processing, application and real-time cores, high-speed networking and security features in a safety-oriented platform. That makes it relevant to demanding edge systems, while leaving performance, power, safety qualification and software readiness dependent on the specific implementation.
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