Recommended Free Tools
Europe’s DARE SGA1 program is investing €239,995,859.50 in a European-led high-performance-computing (HPC) platform based on RISC-V processors, accelerators, chiplet packaging and supporting software. The often-quoted “$260 million” is a rounded conversion of the project’s total cost—not a €240 million European Union grant. The European Commission lists an EU contribution of €102,262,283.43, with €137,733,576.07 from other project financing.
Coordinated by the Barcelona Supercomputing Center, SGA1 runs from March 1, 2025, through February 29, 2028. It is intended to deliver three RISC-V-based chiplets and the software needed to make them useful in future European supercomputers and AI systems. The broader DARE framework is shown by EuroHPC as extending through February 2030.
What DARE is—and what it is not
DARE stands for Digital Autonomy with RISC-V in Europe. DARE SGA1 is the first specific grant agreement in a larger, multi-phase effort to develop European HPC technologies. It is not a single finished processor, a commercial product launch or a European semiconductor-fabrication project.
The first phase is designed to develop and tape out three chiplets, integrate them into a usable compute platform and create a co-designed software stack. The European Commission’s project record identifies grant agreement 101202459 and Barcelona Supercomputing Center as coordinator. DARE’s own materials describe a 38-partner consortium, while the CORDIS participant record lists 44 participants for the grant record; those counts likely reflect different ways of counting organizations and linked participants.
Do these 3 things before closing this tab:
1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minute#1 Best Overall
- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Participants include companies, universities and research institutes. Codasip leads the general-purpose processor, Openchip the vector accelerator, and Axelera AI the AI-inference accelerator. imec and Forschungszentrum Jülich/Jülich Supercomputing Centre are among the organizations identified in technical leadership and HPC roles.
Project information is available from the European Commission’s CORDIS record, the EuroHPC Joint Undertaking and the DARE project site.
What the three chiplets are intended to do
| Chiplet | Lead organization | Intended role |
|---|---|---|
| Vector accelerator | Openchip | High-precision HPC calculations and emerging data-parallel workloads |
| General-purpose RISC-V processor | Codasip | HPC-class CPU work, scientific computing, AI control tasks and big-data processing |
| AI-inference accelerator | Axelera AI | Inference for HPC, data-centre and enterprise AI systems |
Vector acceleration for scientific workloads
Openchip’s vector component is aimed at workloads in which the same operation is applied across many data elements. That includes numerical simulation, scientific modelling and other high-precision HPC tasks. Vector hardware can deliver substantial throughput when applications and memory systems are tuned for it, but the project has not yet published production performance results.
A configurable general-purpose processor
Codasip is responsible for a configurable and customizable RISC-V processor for HPC-class applications. RISC-V’s open instruction-set architecture lets implementers define extensions and tailor a processor rather than relying only on a fixed commercial CPU design. That flexibility is strategically useful to European system builders, although it does not by itself guarantee competitive performance, cost or software maturity.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
An accelerator for AI inference
Axelera AI is developing the AI accelerator chiplet. Trade coverage reported potential funding of up to approximately €61.6 million for Axelera’s work, subject to project deliverables. The planned design is intended to extend Axelera’s digital in-memory-computing approach beyond existing edge-AI products toward HPC, data-centre and enterprise inference. The reported amount is not evidence that a finished accelerator is already commercially available.
Why DARE uses chiplets
Instead of putting every function on one very large die, DARE plans to combine separate processor and accelerator chiplets in a package. The CORDIS description points to potential cost and manufacturing-yield benefits and to avoiding some reticle-size limits that constrain very large monolithic dies.
Potential benefits
- Smaller dies can improve yield because a defect is less likely to make an entire large die unusable.
- Different functions can use different process technologies, allowing dense logic, memory interfaces or analogue elements to be optimized separately.
- System builders can pair a general-purpose processor with vector or AI acceleration suited to a particular workload.
- Modular designs may make later upgrades easier than replacing a complete monolithic processor.
System-level costs and risks
- Chiplet-to-chiplet links add packaging, signalling and validation complexity.
- Latency and memory bandwidth can limit performance even when individual chiplets are fast.
- Advanced packaging, power delivery, thermal management and reliability must work across the complete package.
- Testing and yields become package-level problems rather than only die-level problems.
- Software must schedule work across heterogeneous CPU, vector and AI components.
A chiplet is therefore not a standalone product. The package, board, firmware, drivers, compiler, libraries and application support determine whether it can serve a supercomputing centre.
The software stack may decide whether the silicon is useful
DARE is intended to develop hardware and software in parallel, using emulation and simulation before physical chips are available. The planned stack includes compiler support, runtimes, drivers, libraries, workload distribution and application portability for both AI and non-AI workloads.
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
For HPC users, practical integration matters as much as an instruction-set choice. Existing applications depend on mature compilers, optimized numerical libraries, MPI implementations, accelerator programming models, debuggers, profilers and schedulers. Porting them to a heterogeneous RISC-V platform can require substantial engineering and performance tuning.
The project’s application-led approach is meant to expose these issues early. Success would mean that European research institutions can compile, debug, schedule and run representative workloads across the CPU, vector and inference components without rewriting every application for a single demonstration.
What the €240 million figure actually covers
| Item | Amount or date |
|---|---|
| Total SGA1 project cost | €239,995,859.50 |
| EU contribution | €102,262,283.43 |
| Other project financing | €137,733,576.07 |
| Grant agreement | 101202459 |
| SGA1 start | March 1, 2025 |
| SGA1 end | February 29, 2028 |
The figures come from the CORDIS financial record. The headline’s $260 million is a rounded dollar equivalent of the roughly €240 million total project investment. It should not be described as $260 million paid by the EU budget. An earlier trade report also identified approximately €34 million from Spain’s Ministry of Science, Innovation and Universities as part of partner-side financing; that amount should be understood within, not added on top of, the complete CORDIS total.
EuroHPC displays a broader DARE period from March 1, 2025, to February 28, 2030. That longer range refers to the wider framework, whereas the dates in the table apply specifically to SGA1.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
What “RISC-V sovereignty” means in practice
RISC-V is an open instruction-set architecture. It can reduce dependence on a proprietary ISA owner and give implementers more control over extensions and processor design. DARE also treats open-source software and chiplet integration as parts of its autonomy strategy.
Digital autonomy is layered rather than absolute:
- Instruction-set sovereignty: Europe is not tied to a proprietary instruction-set licensor.
- Microarchitecture sovereignty: European companies can design the processor implementations.
- IP sovereignty: Some interface, memory and other blocks may still be licensed from outside Europe.
- Manufacturing sovereignty: Project reporting identifies TSMC N4C for advanced-node fabrication, so leading-edge wafer production remains external.
- Packaging sovereignty: Advanced packaging capacity may also depend on suppliers outside Europe.
- Software sovereignty: Compilers, runtimes, drivers, libraries and applications must remain maintainable by European institutions.
- Deployment sovereignty: European supercomputing centres must actually be able to procure and operate the systems.
The CORDIS reporting also mentions third-party IP for HBM, LPDDR and PCIe. DARE can therefore increase European control over architecture, integration knowledge and software without making every component or manufacturing step European-controlled.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why Europe considers the effort strategically important
Buying established processors and accelerators can provide near-term performance and mature software, but it leaves public institutions exposed to vendor road maps, licensing terms, export controls, supply disruptions and geopolitical decisions. DARE trades some short-term certainty for greater long-term control over designs and system direction.
That trade-off has limits. A European RISC-V platform could be strategically valuable while initially trailing leading commercial systems in performance, ecosystem breadth, support and total cost of ownership. The size of the grant says nothing by itself about eventual competitiveness.
Free tools Windows power users keep installed
One-click scans. No signup required.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
How DARE’s success should be judged
The project’s meaningful tests are engineering and adoption milestones, not the announcement value:
- Successful tape-outs of the vector, general-purpose and AI chiplets.
- Working silicon and reliable package integration.
- Measured performance and energy efficiency on representative HPC and AI applications.
- Compilers, runtimes, drivers, libraries and debugging tools usable by application teams.
- Integration with European supercomputer prototypes or production systems.
- A credible route from research silicon to repeatable manufacturing and supply.
- European companies willing to sell boards, systems or processor IP with long-term support.
- Evidence that the platform reduces strategic dependence rather than merely adding another research architecture.
The official objective is to develop and tape out three chiplets and prepare a technical roadmap for the next phase. It is not a claim that those milestones, final benchmarks, production availability or customer adoption have already been achieved.
Bottom line for HPC and semiconductor readers
DARE is significant because it attempts to build a complete European HPC technology base: configurable RISC-V compute, specialized acceleration, chiplet integration and the software needed to deploy them. The accurate headline is a roughly €240 million project with about €102.3 million in EU funding, not a €240 million EU cheque. Its autonomy is also partial: design and software control may become more European while advanced fabrication, packaging and selected IP remain global dependencies.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
